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MX98905B
FEATURES
* Control - Controller and integrated bus interface total solution for IEEE 802.3, 10BASE5, 10BASE2 and 10BASE-T - Software-compatible with industry standard Ethernet adapters: * Novell(R)'s NE 2000 * Western Digital/SMC's (8003E, 8003EBT, 8013EBT) - Selectable buffer memory size - No external bus logic or drivers - Integrated controller, MCC and transceiver - Full IEEE 802.3 AUI interface - Single 5V supply - Software-compatible with DP8390, DP83901 and DP83902 - Efficient buffer management implementation * MCC module (Manchester Code Converter, also called ENDEC) - 10 Mbit/s Manchester encoding/decoding - Squelch on receive and collision pairs * TPI module (10BASE-T) transceiver - Transmitter and receiver functions - Collision detect, heartbeat and jabber - Selectable link integrity test or link disable - Polarity detection/correction * Provides more powerful functions than NS DP83905 - Supports 15 I/O bases instead of 7 - Direct ID PROM access through I/O port instead of through remote DMA - Auto configuration function-supported makes jumperless more powerful - Solution for multiple LAN cards I/O bases conflict problem to make manufacture more efficient. - Supports "write ID back to EEPROM" function instead of just writing configuration back to EEPROM to make manufacture more efficient. - Modify current configurations without turning off power - Variety of EEPROM supported
GENERAL DESCRIPTION
The MX98905 is designed for easy implementation of CSMA/CD local area networks, which include Ethernet(R) (10BASE5), Thin Ethernet (10BASE2), and Twisted-pair Ethernet (10BASE-T). The Media Access Control (MAC) and Encode-Decode (ENDEC) are provided with an AUI interface. The 10BASE-T transceiver functions according to the IEEE 802.3 standards, and the MX98905 10BASE-T transceiver operations in compliance with the IEEE standard. The functional block of the MX98905 consists of the integration of the entire bus interface for PC-AT(R) (Industry Standard Architecture, ISA) bus-based systems, receiver, transmitter, collision, heartbeat, loopback, jabber, and link integrity blocks. When combined with equalization resistors, the transceiver transmits or receives filters, and pulse transformers provide physical interface from the ENDEC module of the MX98905 and the twisted-pair medium. When software and hardware are properly configured, the MX98905 can be set to be compatible with either the NE2000 or EtherCard PLUS16TM. All bus drivers and control logic are integrated inside the chip to reduce LAN card cost and area. Manchester encoding and decoding is made possible through the integrated ENDEC by means of a differential transceiver and phase lock loop decoder at 10 Mbit/sec. Collision detect translator and diagnostic loopback capability are included in this process. Interfacing directly with the transceiver module, the ENDEC module also provides a fully IEEE-compliant AUI (Attachment Unit Interface) to connect with other media transceivers. The Media Access Control function, provided by the Ethernet Network Control (ENC) module, effects an efficient packet transmission and reception control through unique dual DMA channels and an internal FIFO. To lessen board cost and area overheads, bus arbitration and memory control logic are integrated. Designed for easy interface with other transceivers by means of the AUI interface, the MX98905 provides a thorough single chip solution for 10BASE-T IEEE 802.3 network. Constraints of CMOS processing require that isolation, whether capacitive or inductive, be used at the AUI differential signal interface for 10BASE5 and 10BASE2 applications.
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REV. 1.3, NOV 20 ,1995
P/N: PM0365
MX98905B
Note: TRI-STATE(R) is a registered trademark of National Semiconductor. PC-AT(R) is a register trademark of International Business Machines Corp. Novell(R) is a registered trademark of Novell Inc. EtherCard PLUSTM and EtherCard PLUS 16TM are trademarks of standard Microsystems Corp. Ethernet(R) is a registered trademark of Xerox Corp.
P/N: PM0365
2
REV. 1.3, NOV 20 ,1995
MX98905B
PIN CONFIGURATION
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
SMWRL SMRDL IOWRL IORDL GND SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 VCC SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 GND SA3 SA2 SA1 SA0 ISACLK INT3 INT2 INT1 INT0 BALE VCC M16L GND IO16L SBHEL LA23 LA22
VCC AEN CHRDY GND GND RESET SD0 SD1 GND SD2 SD3 VCC SD4 SD5 GND SD6 SD7 GND VCC GND TXM TXP VCC VCC RXM RXP CDM CDP GND RXIP RXIM VCC TXODM TXOP TXOM TXODP VCC GND GND VCC
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
MX98905B
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
LA21 LA20 LA19 LA18 LA17 MRDL MWRL SD8 SD9 GND SD10 SD11 VCC SD12 SD13 GND SD14 SD15 LOWPWR ATXT GND VCC MEMD0 MEMD1 MEMD2 MEMD3 GND MEMD4 MEMD5 MEMD6 MEMD7 VCC MEMD8 MEMD9 MEMD10 MEMD11 GND MEMD12 MEMD13 MEMD14
P/N: PM0365
GDLINKL POLEDL COLEDL RXLEDL TXLEDL GND X1 X2 VCC THIN TEST BSCLK VCC GND MEMA15 MEMA14 MEMA13 MEMA12 MEMA11 MEMA10 MEMA9 MEMA8 GND VCC MEMA7 MEMA6 MEMA5 MEMA4 MEMA3 MEMA2 MEMA1 MSWRL MSRDL RCS2L GND RCS1L BPCSL EECS EECONFIG MEMD15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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REV. 1.3, NOV 20 ,1995
MX98905B
PIN DESCRIPTIONS
A. ISA BUS INTERFACE
SYMBOL SA0-SA19 PIN TYPE I PIN NUMBER 94-97, 99-106, 108-115 DESCRIPTION LATCHED ADDRESS BUS: Low-order bits of the system's 24-bit address bus. These lines are enabled onto the bus when BALE is high and latched when BALE is deasserted. The MX98905 uses these bits to decode the boot PROM address and internal registers. In shared memory mode, they are used to decode accesses to memory of the MX98905. UNLATCHED ADDRESS BUS: High-order 7 bits of the 24-bit system address bus. These lines are valid on the falling edge of BALE. The MX98905 uses these bits to decode shared memory address in shared memory mode. The validity of M16L depends on these signals only. SYSTEM DATA BUS: 16-bit system data bus. Used to transfer data between the system and the MX98905.
LA17-LA23
I
76-82
SD0-SD15
I/O
127, 128, 130,
131, 133, 134,
136, 137, 73, 72 70, 69, 67, 66, 64, 63 BALE I 88 BUS ADDRESS LATCH ENABLE: Active-high signal. Used to latch valid addresses from the current Bus Master on the falling edge of BALE. SYSTEM BUS HIGH ENABLE: Active-low. Indicates that the system expects a transfer on the address on the bus is 16 bits wide. 16-BIT I/O TRANSFER: Active-low. In I/O mode this signal indicates that the MX98905 is responding to a 16-bit I/O access by driving 16 bits of data on SD0-SD15. 16-BIT MEMORY TRANSFER: Active-low. MEMORY WRITE STROBE: Active-low. System uses this signal to write to the memory map of the MX98905. MEMORY READ STROBE: Active-low. System uses this signal to read from the memory map of the MX98905. LOW MEMORY STROBES: Active-low. The MX98905 uses MRDL and MWRL in 16-bit memory mode and will use SMRDL and SMRL in memory mode when ATXT is low (8-bit mode). Note that SMRDL and SMWRL are also used to access the BOOT PROM. I/O WRITE STROBE: Active-low. Strobe from system to write to the I/O Map of the MX98905. I/O READ STROBE: Active-low. Strobe from system to read from the I/O Map of the MX98905.
SBHEL
I
83
IO16L
O
84
M16L MWRL
O I
86 74
MRDL
I
75
SMRDL, SMWRL
I
119, 120
IOWRL
I
118
IORDL
I
117
P/N: PM0365
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REV. 1.3, NOV 20 ,1995
MX98905B
A. ISA BUS INTERFACE (Continued)
SYMBOL RESET PIN TYPE I PIN NUMBER 126 DESCRIPTION RESET : Active high. Used to reset all devices on the bus. The MX98905 will recognize this signal only when the duration of this signal is larger than 400 ns. CHANNEL READY: Used to insert wait states into system accesses. DMA ACTIVE: Indicates that the address lines are driven by a DMA controller. INTERRUPT REQUEST: Activation or not of these 4 signals is determined by Configuration Registers A and C. They can be used to either directly drive the interrupt lines or used as a 3-bit code with strobe to generate up to 8 interrupts. 8/16 BIT SLOT SELECT: Indicates that the MX98905 is in 8- or 16bit ISA bus. It is in 16-bit mode when ATXT is high ATXT has internal pulldown register; if left unconnected, 8-bit mode is the default mode. ISA CLOCK: Clock from ISA bus.
CHRDY AEN
O I
123 122
INT0-INT3
O
89-92
ATXT
I
61
ISACLK
I
93
P/N: PM0365
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REV. 1.3, NOV 20 ,1995
MX98905B
B. NETWORK INTERFACE
SYMBOL POLEDL PIN TYPE O PIN NUMBER 2 DESCRIPTION POLARITY LED: Active-low signal. When the MX98905 detects seven consecutive link pulses or three consecutive received packets with reversed polarity, POLEDL is asserted. TRANSMIT LED: Active-low signal. It is asserted for approximately 50ms whenever the MX98905 transmits data in either AUI or TPI modes. RECEIVE LED: Active-low signal. An open-drain output. It is asserted for approximately 50ms whenever valid received data is detected while in AUI or TPI modes. COLLISION LED: An open-drain active-low signal. It is asserted for approximately 50ms whenever collision is detected while in AUI or TPI modes. GOOD LINK LED: An open-drain active-low signal. Used to display link integrity status. OFF (when high): A. MX98905 is in AUI mode B. MX9805E is in TPI mode, link testing is enabled and link integrity is bad. ON (when low): A. Link testing is disabled B. Link testing is enabled and link integrity is good. X1 X2 I O 7 8 Crystal or external oscillator input. CRYSTEL FEEDBACK OUTPUT: Used in crystal connection only. Should be left completely unconnected when using an oscillator module. THIN CABLE: Active-high signal. It is high when the MX98905 is configured for thin cable (program PHY1 and PHY0 of Configuration B). This signal can be used to turn on the DC-DC converter required by thin Ethernet. TWISTED-PAIR TRANSMIT OUTPUTS: These high-drive CMOS level outputs are resistively combined external to the chip to produce a differential output signal with equalization to compensate for intersymbol interference (ISI) on the twisted-pair medium.
TXLEDL
O
5
RXLEDL
O
4
COLEDL
O
3
GDLINKL
O
1
THIN
O
10
TXODP, TXOM, TXOP, TXODM
O
156-153
P/N: PM0365
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REV. 1.3, NOV 20 ,1995
MX98905B
B. NETWORK INTERFACE (Continued)
SYMBOL RXIP, RXIM PIN TYPE I PIN NUMBER 150-151 DESCRIPTION TWISTED-PAIR RECEIVE INPUTS: These inputs feed a differential amplifier which passes valid data to the MCC module. AUI TRANSMIT OUTPUT: Differential driver which sends the encoded data to the transceiver. The outputs are source follower which requires 270 W pulldown resistors. AUI RECEIVE INPUTS: transceiver. Differential receive input pair from the
TXM, TXP
O
141-142
RXM, RXP
I
145-146
CDM, CDP
I
147-148
AUI COLLISION INPUTS: Differential collision pair input from the transceiver cable.
P/N: PM0365
7
REV. 1.3, NOV 20 ,1995
MX98905B
C. EXTERNAL MEMORY SUPPORT
SYMBOL MEMD0-7 CA0-7 DO, DI, SK PIN TYPE I/O PIN NUMBER 58-55 DESCRIPTION MEMORY SUPPORT DATA BUS; CONFIGURATION REGISTER A INPUT; EEPROM SIGNALS. MEMD0-7 : These pins can be used to access external memory (RAM) and boot PROM while RESET is inactive. CA0-7: When RESET is active more than 400 ms, Configuration Register A is loaded with the value on these pins on the falling edge of RESET signal. These 8 bits have internal pulldown resistors, hence if the pin is left unconnected the corresponding register bit is 0. DO, DI, SK: When RESET goes from an active to an inactive level, the MX98905 will read the contents of an EEPROM. At this moment, DO = MEMD0, DI = MEMD1 and SK = MEMD2. The value read from EEPROM will be stored in Configuration Registers and PROM space. MEMORY SUPPORT DATA BUS; CONFIGURATION REGISTER B INPUT. MEMD8-15 : These pins can be used to access external memory when RESET is inactive. CB0-7 : When RESET is active more than 400 ms, Configuration Register B is loaded with the value on these pins on the falling edge of RESET signal. These 8 bits have internal pulldown registers, hence if the pin is left unconnected the corresponding register bit is 0. MEMORY SUPPORT ADDRESS BUS; CONFIGURATION REGISTER C INPUT. MEMA1-8 : These pins can be used to drive external memory address bus when RESET is inactive. CC0-7 : When RESET is active more than 400 ms, Configuration Register C is loaded with the value on these pins on the falling edge of RESET signal. For application without EEPROM (i.e. EECONFIG is low) and try to load configuration data to CC from these eight pins, external resistor is necessary. MEMORY SUPPORT ADDRESS: These pins can be used to drive external memory address bus when RESET is inactive. When the memory is only 8 bits wide (single RAM) and the MX98905 is in compatible mode, A0 will appear on A13; and on A15 in noncompatible mode. MEMORY SUPPORT BUS READ: Strobes data from the external RAM into the MX98905 through the memory support data bus. MEMORY SUPPORT BUS WRITE: Strobes data from the MX98905 into the external RAM via the memory support data bus. BOOT PROM CHIP SELECT: Active-low signal for selecting the Boot PROM.
MEMD8-15
I/O
48-45
MEMA1-8
I/O
31-25, 22
MEMA9-15
O
21-15
MSRDL
O
33
MSWRL
O
32
BPCSL
O
37
P/N: PM0365
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REV. 1.3, NOV 20 ,1995
MX98905B
C. EXTERNAL MEMORY SUPPORT (Continued)
SYMBOL RCS1L PIN TYPE O PIN NUMBER 36 DESCRIPTION RAM CHIP SELECT 1 : Active-low signal to drive the CS signal of the external RAM on the lower half of the memory-supported data bus. RAM CHIP SELECT 2: Active-low signal to drive the CS signal of external RAM on the upper half of the memory-supported data bus. EEPROM CHIP SELECT: Active-high signal to drive the CS signal of the external EEPROM. CONFIGURE FROM EEPROM: The MX98905 will NOT load configurations from EEPROM if this pin is low during power-on reset. INTERNAL BUS CLOCK: This pin controls the speed of the controller DMA function. When CLKSEL of configuration C is set low, this pin should be tied to ground.
RCS2L
O
34
EECS
O
38
EECONFIG
I
39
BSCLK
I
12
D. LOW POWER SUPPORT
SYMBOL LOWPWR PIN TYPE I PIN NUMBER 62 DESCRIPTION LOW POWER: When it is high, the MX98905 enters its low-power mode. This pin should be tied to ground for normal operation.
E. TEST SUPPORT
SYMBOL TEST PIN TYPE I PIN NUMBER 11 DESCRIPTION TEST: This pin is only used for industry test. It should be left unconnected in normal operation (because it has internal pulldown resistor).
P/N: PM0365
9
REV. 1.3, NOV 20 ,1995
MX98905B
F. POWER SUPPLY PINS
SYMBOL VCC PIN TYPE I PIN NUMBER DESCRIPTION
160, 157, 152, 5V POWER SUPPLY PIN. 144, 143, 9, 59, 49, 24, 13, 132, 121, 107, 87, 68,139 159, 158, 149, GND SUPPLY PIN. 140, 138, 6, 60, 54, 44, 35, 23, 14, 135, 129, 125, 124, 116, 98, 85, 71, 65
GND
I
P/N: PM0365
10
REV. 1.3, NOV 20 ,1995
MX98905B
FUNCTIONAL DESCRIPTION
1. I/O BASES DETERMINATION The I/O bases are determined by 6 bits in the MX98905. They are: IOAD2-0 in Configuration A (CA); PAGE and IOBEN in Hidden Configuration Register (HCFR) and HCFRE in Hidden Command Register (HCMR). For details about HCMR and HCFR (Registers provided by The following are the I/O bases mapping:
TABLE 1. I/O BASES MAPPING HCMR HCFRE 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 HCFR IOBEN X X X X X X X X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 HCFR PAGE X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 IOAD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CA IOAD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 IOAD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 I/O BASE 300H Not supported 240H 280H 2C0H 320H 340H 360H 300H Not supported 240H 280H 2C0H 320H 340H 360H 300H Not supported 240H 280H 2C0H 320H 340H 360H
the MX98905 only) see Register Description. User can directly modify the value of PAGE and IOAD2-0 to change I/O base or use AUTO configuration feature provided by the MX98905. See Enhanced mode description for details about AUTO configuration.
P/N: PM0365
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REV. 1.3, NOV 20 ,1995
MX98905B
HCMR HCFRE 1 1 1 1 1 1 1 1 HCFR IOBEN 1 1 1 1 1 1 1 1 PAGE 1 1 1 1 1 1 1 1 IOAD2 0 0 0 0 1 1 1 1 CA IOAD1 0 0 1 1 0 0 1 1 IOAD0 0 1 0 1 0 1 0 1 I/O BASE 380H 3A0H 3C0H 3E0H 200H 220H 2A0H 2E0H
HCFRE, IOBEN and PAGE are powered on low if software driver doesn't alter the value of these bits. The I/O bases of the MX98905 are fully compatible with DP83905.
P/N: PM0365
12
REV. 1.3, NOV 20 ,1995
MX98905B
2. SHARED MEMORY COMPATIBLE MODE This mode is compatible with the EtherCARD PLUS16. I/ O address mapping and Memory mapping will be described subsequently. After I/O Base is determined, the following structure appears:
8000H 0000H D15 8Kx16 BUFFER RAM D0
4000H ALIASED BUFFER RAM
2.1 I/O Address Mapping
FIGURE 2. SHARED MEMORY MODE REGISTER MAPPING
IORDL BASE + 00H BASE + 01H AT DETECT CONTROL1 IOWRL
FFFFH C000H
ALIASED BUFFER RAM
ALIASED BUFFER RAM
BASE + 05H
CONTROL2
FIGURE 4. SHARED MEMORY MODE HOST MEMORY MAP FOR 8 KBYTES BUFFER RAM
D15 BASE + 0000H D0
BASE + 08H PROM BASE + 0FH BASE + 10H MX9890 CORE REGISTERS BASE + 1FH
8Kx8 BUFFER RAM BASE + 3FFFH
The AT Detect register indicates whether the MX98905 is in an 8- or 16-bit slot. The MX98905 uses the falling edge of RESET to latch the value shown on ATXT to determine the value of ATDET. Address 08H to 0FH are specified as PROM space. The contents of PROM are loaded from EEPROM during power-on reset. User should program the EEPROM to contain these value. In enhanced mode of the MX98905, the contents of PROM can be written back to EEPROM. See enhanced mode description for details.
FIGURE 5. SHARED MEMORY MODE HOST MEMORY MAP FOR 16 KBYTES BUFFER RAM
D15 BASE + 0000H 16Kx8 BUFFER RAM BASE + 7FFFH D0
2.2 Memory Address Mapping
FIGURE3. SHARED MEMORY MODE ENC CORE MEMORY MAP
P/N: PM0365
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REV. 1.3, NOV 20 ,1995
MX98905B
The 8 kwords of memory can be accessed directly by the host system in the same manner as any other memory. Typically the programmer can remove data from this buffer using a "MOV" or "MOVSW" instruction. In compatible mode, data located at address 4000h7FFFH, 8000H-BFFFH and C000H-FFFFH is just the mirror of contents located at 0000H-3FFFH.
2.3 Configuration vs. Operation
MEMW 0 0 1 1 0 0 1 1 COMP 0 0 0 0 1 1 1 1 SIZE 8K 8K 16K 16K 32K 32K 64K 64K ATDET 0 1 0 1 0 1 0 1 MX98905 ACCESS MODE Byte Byte Byte/Word Byte/Word Byte Byte Byte/Word Byte/Word HOST ACCESS MODE Byte Byte Byte Byte/Word Byte Byte Byte Byte/Word
2.4 SRAM Size vs. MEMA[15:1]
SRAMSIZE 8K 16K 32K 64K MEMA15 0 0 A0 A15 MEMA14 1 1 A14 A14 MEMA13 A0 A13 A13 A13 RCS1L Even/Odd Even Even/Odd Even RCS2L X Odd X Odd
P/N: PM0365
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REV. 1.3, NOV 20 ,1995
MX98905B
3. SHARED MEMORY NON-COMPATIBLE MODE The difference between compatible and noncompatible mode is that the non-compatible mode maps a full 64 kbytes of RAM into the PC's memory address space instead of 8 kbytes. The I/O map for both modes is the same. 4.2 Memory Address Mapping
FIGURE 7. I/O MODE MEMORY MAP
D15 0000H PROM 001FH
D0
4. 16-BIT I/O PORT COMPATIBLE MODE This mode is compatible with the Novel NE2000. I/O address mapping and Memory mapping will be shown in the following subsection. After I/O base is determined, the following structure appears: 4.1 I/O Address Mapping
FIGURE 6. I/O MODE I/O PORT MAP
C000H
D15 BASE + 00H MX9890 CORE REGISTERS BASE + 0FH BASE + 10H D0
ALIASED PROM 4000H 8Kx16 BUFFER RAM 7FFFH 8000H ALIASED PROM
ALIASED BUFFER RAM FFFFH
DATA TRANSFER PORT BASE + 17H BASE + 18H
The MX98905 Controller has a 64K address range, but only does partial decoding on these devices. The PROM data is mirrored at all decodes up to 4000H and the entire map is repeated at 8000H. In order to access either the PROM or the RAM, the user must initiate a Remote DMA transfer between the I/O port (see I/O map) and the memory. Address 00H to 1FH are specified as the PROM space to make the MX98905 compatible with NE2000. Similar to shared memory map, this is actually an array of 8-bit registers which are loaded from EEPROM during power-on reset. User should prepare data in the EEPROM as show in the format. For user's convenience, the MX98905 provides an enhanced mode to facilitate software to access the contents of ID PROM -- Read ID PROM through I/O port. User can refer to Enhanced mode description for details.
RESET PORT BASE + 1FH
The registers within this area are 8 bits wide, but the data transfer port is 16 bits wide. By programming the ENC's internal registers, the user can issue Remote DMA to transfer data between the data port and the external memory.
P/N: PM0365
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REV. 1.3, NOV 20 ,1995
MX98905B
4.3 PROM Map
TABLE 2. PROM LOCATION 00H 01H 02H 03H 04H 05H 06H-0DH 0E-0FH 10-15H 16-1DH 1E-1FH LOCATION CONTENTS EtherNet Address 0 (MSB) EtherNet Address 1 EtherNet Address 2 EtherNet Address 3 EtherNet Address 4 EtherNet Address 5 00H 57H EtherNet Address 0 thru 5 Reserved 42H
BUFFER RAM 0000H PROM 00FFH 0100H D15 D0
6. I/O PORT NON-COMPATIBLE MODE Although this mode is similar to Novell's NE2000, it also allows the user to use the full 64 kbytes of address space except for an initial page for the PROM. I/O map is the same as compatible mode. Memory map is shown below:
FIGURE 9. I/O MODE NON-COMPATIBLE MODE MEMORY MAP
The upper two addresses of the PROM store contain bytes that identify whether the MX98905 Controller is in 8- or 16-bit mode. For 16-bit mode the values of these bytes are 57H; for 8-bit mode they both contain 42H. Software driver can read these two bytes to determine whether the Controller is in 8- or 16-bit mode.
FFFFH
Although the PROM occupies 256 bytes, it is only 16 bytes long. There is a partial decode inside the MX98905 so the PROM is mirrored at 16 addresses in this region.
5. 8-BIT I/O PORT COMPATIBLE MODE 7. POWER-ON RESET OPERATION In 8-bit I/O port compatible mode, the I/O mapping is the same as in 16-bit mode. The memory map for 8-bit I/O port compatible mode is shown below:
FIGURE 8. I/O MODE 8-BIT MEMORY MAP
D15 0000H PROM 001FH D0
When the duration of RESET signal is longer than 400ns, the MX98905 will read configurations from EEPROM depending on the value shown on EECONFIG pin. User should prepare all the data the MX98905 needs in the EEPROM before switching on the PC. The following table shows the format of EEPROM:
UNUSED
4000H 5FFFH 8Kx16 BUFFER RAM
P/N: PM0365
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REV. 1.3, NOV 20 ,1995
MX98905B
TABLE 3. EEPROM DATA MAPPING
D15 0FH 0EH NOT USED CONFIG. B * * * 08H 07H 42H 57H * * * 03H RESERVED (CHECKSUM) 02H 01H 00H ETEHR ADD 5 ETHER ADD 3 ETEHR ADD 1 CONFIG. C CONFIG. A * * * 42H 57H * * * RESERVED (BOARD TYPE) ETHER ADD 4 ETEHR ADD 2 ETEHR ADD 0 D0
except the RESET signal. On the falling edge of RESET signal, the MX98905 will load data shown on MEMD0-7, MEMD8-15 and MEMA1-8 into Configuration Register A, B and C, respectively. The value loaded from jumper will overwrite the default value. Figure 10 shows the example for jumper configuration. After loading jumper value into relative Configuration Registers, the MX98905 will execute EEPROM operation, which depends on the value of EECONFIG. If EECONFIG is high, then both the configuration and ID PROM data will be loaded into the MX98905; otherwise, only ID PROM data is loaded. 7.2 EEPROM Operation During EEPROM operation, all internal registers are inaccessible. If EECONFIG is high, then the configurations loaded from EEPROM will overwrite the value loaded from jumper selection. Configurations loaded from EEPROM will be stored in Configuration Registers and Ether ID will be stored in PROM space inside the MX98905 (refer to PROM MAP for details).
values shown on parentheses are for Shared memory map only. For the shared memory mode, the two's complement of these eight bytes (00-03H) should be equal to FFH. High byte of 0FH is not used in NS DP83905 compatible mode, but the value will be loaded into Hidden ConFiguration Register (HCFR) inside the MX98905 in enhanced mode. See Enhanced mode description for details.
7.2.1 Load Configurations from EEPROM When EECONFIG is set to high, configurations stored in EPPROM will be loaded into MX98905. After loading configurations fom EEPROM, following sequence depends on the value of ATXT: ATXT= 1 : 00H-07H ATXT= 0 : 00H-06H, 08H EECONFIG = 1 : OEH (Configuration A, B), OFH DWID = 1 (Configuration C),00H - 02H (Ether Address 0 theu 5) and 03H - 07H
EECONFIG = 1 : OEH (Configuration A, B), OFH DWID = 0 (Configuration C),00H - 02H (Ether Address 0 true 5)and 03H - 06H and 08H (data 42H) 7.2.2 Without loading configurations from EEPROM When EECONFIG is set to low, configrations stored in EEPROM will NOT be loaded into the MX98905 depends on the value of ATXT: ATXT = 1 : 00H-07H ATXT = 0 : 00H-06H,08H
7.1 Valid Power-On Reset The MX98905 is equipped with a filter to screen out RESET signal whenever its duration is less than 400ns. The default value of each Configuration Register is: Configuration Register A : 39H Configuration Register B : 00H Configuration Register C : 00H When RESET is active more than 400ns, the MX98905 will recognize such action and begin its power-on reset algorithm. At this moment, all I/O will be disabled
P/N: PM0365
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REV. 1.3, NOV 20 ,1995
MX98905B
8. STORING CONFIGURATION BACK TO EEPROM To write configuration into the EEPROM, user must follow the procedure specified below: EEPROM_STORE ( ) { Disable_All_Interrupts ( ) ; value = READ (CB) ; value = value & GDLINK ; value = value I EESTORE ; write (CB, value) ; / / Issue EESTORE / / EESTORE algorithm starts Read (CB) ; write (CB, value_for_CA) ; / / write new / /into CA through CB write (CB, value_for_CB) ; / / write CB write (CB, value_for_CC) ; / / write new value into CC through CB while (value & EESTORE) { value = Read(CB) ; wait ( ) ; } Enable_All_Interrupts ( ) ;
P/N: PM0365
18
REV. 1.3, NOV 20 ,1995
MX98905B
FIGURE 10. EXAMPLE OF JUMPER CONFIGURATION
MEMA8 VDD MEMA7 RESISTOR MEMA6 IN RESISTOR IN RESISTOR IN RESISTOR IN RESISTOR OUT OUT OUT OUT RESISTOR MEMA5 RESISTOR MEMA4 RESISTOR MEMA3 RESISTOR MEMA2 RESISTOR MEMA1 RESISTOR RESISTOR
DATA LOADED TO CC 1EH
MEMD15 MEMD14 MEMD13 MEMD12 IN RESISTOR IN RESISTOR IN RESISTOR MEMD8 OUT OUT OUT MEMD11 MEMD10 MEMD9
DATA LOADED TO CB 0EH
IN RESISTOR IN RESISTOR IN IN IN RESISTOR IN RESISTOR RESISTOR RESISTOR
OUT OUT OUT OUT OUT OUT
MEMD7 MEMD6 MEMD5 MEMD4 MEMD3 MEMD2 MEMD1 MEMD0
DATA LOADED TO CA FCH
Note:Pull down resistors(4.7Ky~10Ky) are required to be connected to MEMA8~MEMA1.
P/N: PM0365
19
REV. 1.3, NOV 20 ,1995
MX98905B
After EEPROM_STORE is executed, the current configuration will NOT be changed. If user wants to use the new configuration, he should turn the power off and then turn it on to load new configuration into the MX98905 through valid power-on reset. For user's convenience, the MX98905 provides the feature for software programmer to update the current configuration after EEPROM_STORE is executed, i.e., you don't have to switch the power to update the configuration. See Enhanced Description for details. MX98905 or MX98905A, user must follow the procedure described in section 8. In MX98905, a "1" value in ALLWR bit will cause the controller to write CA, CB, CC and ID to EEPROM. While in MX98905A, a "1" value in ALLWR bit will write CA, CB, CC, ID, and the rest of 8 bytes from IDPROM registers. i.e. the entire 16 bytes of IDPROM registers can be written back to EEPROM. The other EEPROM write back command is IDWCMD command whose function remains the same as old version. When loading data from EEPROM during power-on reset, values in IDPROM register byte 15th and 16th are never written back to EEPROM but initialized to correct value according to slot's data width during power-on reset. these two bytes can be modified through software programming.
9. ENHANCED FEATURE FUNCTIONAL DESCRIPTION There are two registers, HCMR and HCFR which control the main fuctions of MX98905's enhaned mode. HCMR is the abbreviation of Hidden Command Register and HCFR for Hidden Configuration Register. Bit assignment and function of each bit of HCMR and HCFR will be fully descibed in REGISTER DESCRIPTIONS. For your quick reference, bit assignments of HCMR and HCFR are shown below before we present the enhanced features of MX98905. The following shows the bit assignment for HCMR:
9.3 Update Current Configuration EEPROM_STORE is Finished
After
RESVD MULTI ALLWR IDECMD AUTO NPGEN PGSEL HCFRE
When NEWCF bit of HCFR is set, the contents of CA, CB and CC will be updated to the value in EEPROM_STORE algorithm after EEPROM_STORE algorithm is finished. USER DOESN'T HAVE TO SWITCH THE POWER TO USE THE NEW CONFIGURATION. 9.4 Access ID PROM Through I/O Port IN NE2000 Compatible When NPGEN is high and PGSEL is low (both in HCMR), the MX98905 is programmed to New Page 0. Contents of ID PROM can be directly accessed through I/O port. Table 4 and Table 5 show the address mapping. 9.5 Auto Configuration The MX98905 provides a powerful feature for programmer to program the LAN card in order to avoid the "IO base is conflict with other add_ on cards" program. When bit 3 (AUTO) of HCMR is set to 1, the MX98905 will change the internal IO base automatically. When software writes to AUTO the first time, the IO base will change to 300H no matter the current IO base is. Susbsequent writing to AUTO bit will make the MX98905 jump to the "next" IO base as described in next paragraph. After AUTO is issued, user can use the information provided below to read the AutoStatus
REV. 1.3, NOV 20 ,1995
Following shows the bit assignment for HCFR
RESVD RESVD RESVD RESVD LOCKE NEWCF PAGE IOBEN
9.1 Load HCFR From EEPROM The high-byte value of address 0FH of EEPROM will be loaded into Hidden ConFiguration Register (HCFR) if a valid power-on reset is detected by the MX98905. HCFR is only active when HCFRE bit of HCMR (Hidden CoMmand Register, supported by the MX98905) is set high. If software doesn't alter the value of HCFRE, the value in HCFR has no effect. In the same way, when EEPROM_STORE algorithm is executed, contents of HCFR will be stored back to EEPROM at the location from where they come. 9.2 16 Bytes IDPROM write back function To write configuration into the EEPROM in either
P/N: PM0365
20
MX98905B
Register (ASR) to determine whether the IO base is conflict with other add_ on card(s) or not. When 15 IO base is not enabled (see HCMR register description for more detail), internal state machine will only support 7 IO bases when AUTO is written; if IOBEN of HCFR is set to high (see HCFR register description for more detail), the internal state machine will alter the value of PAGE of HCFR automatically when further IO base is necessary during auto configuration. The following I/O bases are supported by MX98905. (*) represents that the IO bases are not supported by MX98905 when 15 IO base is not enabled. 200H (*), 220H (*), 240H, 280H,2A0H (*), 2C0H, 2E0H (*), 300H, 320H, 340H, 360H, 380H (*), 3A0H (*), 3C0H (*) , and 3E0H (*) The following IO base and its relative ASR value (shown in parenthses) will be followed after software write an "1" to AUTO bit of HCMR.
P/N: PM0365
21
REV. 1.3, NOV 20 ,1995
MX98905B
TABLE 4. NEW PAGE 0 ADDERSS ASSIGNMENT FOR I/O MAP SA00..3 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH READ PROM BYTE #0 (PB0) PROM BYTE #1 (PB1) PROM BYTE #2 (PB2) PROM BYTE #3 (PB3) PROM BYTE #4 (PB4) PROM BYTE #5 (PB5) PROM BYTE #6 (PB6) PROM BYTE #7 (PB7) PROM BYTE #8 (PB8) PROM BYTE #9 (PB9) PROM BYTE #10 (PB10) PROM BYTE #11 (PB11) PROM BYTE #12 (PB12) PROM BYTE #13 (PB13) PROM BYTE #14 (PB14) PROM BYTE #15 (PB15) WRITE PROM BYTE #0 (PB0) PROM BYTE #1 (PB1) PROM BYTE #2 (PB2) PROM BYTE #3 (PB3) PROM BYTE #4 (PB4) PROM BYTE #5 (PB5) PROM BYTE #6 (PB6) PROM BYTE #7 (PB7) PROM BYTE #8 (PB8) PROM BYTE #9 (PB9) PROM BYTE #10 (PB10) PROM BYTE #11 (PB11) PROM BYTE #12 (PB12) PROM BYTE #13 (PB13) PROM BYTE #14 (PB14) PROM BYTE #15 (PB15)
TABLE 5. NEW PAGE 0 ADDRESS ASSIGNMENT FOR MEMORY MAP SA00..3 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH READ Control 1 AT Detect Reserved Reserved Reserved Control 2 Reserved Reserved PROM BYTE #0 (PB0) PROM BYTE #1 (PB1) PROM BYTE #2 (PB2) PROM BYTE #3 (PB3) PROM BYTE #4 (PB4) PROM BYTE #5 (PB5) PROM BYTE #6 (PB6) PROM BYTE #7 (PB7) WRITE Control 1 Reserved Reserved Reserved Reserved Control 2 Reserved Reserved PROM BYTE #0 (PB0) PROM BYTE #1 (PB1) PROM BYTE #2 (PB2) PROM BYTE #3 (PB3) PROM BYTE #4 (PB4) PROM BYTE #5 (PB5) PROM BYTE #6 (PB6) PROM BYTE #7 (PB7)
P/N: PM0365
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REV. 1.3, NOV 20 ,1995
MX98905B
9.6 Write Network ID Back To EEPROM The programmer has two approaches to store Network ID back to EEPROM. They are: 1. Store Network ID only 2. Store Configuration and Network ID at the same time For case 1, the following procedure should be followed exactly: ID_STORE ( ) { Program_to_new_page_0 ( ) ; / / See Register description if (necessary) Modify_PROM_Byte0_5 ( ) ; Program_to_new_page_1 ( ) ; / / See Register description write (HCMR, '16H') ; / / Issue IDWCMD value = Read (HCMR) ; while (value & IDWCMD) { value = Read (HCMR) ; wait ( ) ; } write (HCMR, '00H') ; / / Back to Normal mode } The following pseudo C code algorithm is for case 2: ALL_STORE ( ) { Program_to_new_page 0 ( ) ; / / See Regsiter description if (necesary) Modify_PROM_BYTE0_7 ( ) ; Program_to_new_Page_1 ( ) ; / / See Register description write (HCMR, '20H') ; / / Enable All Write algorithm EEPROM_STORE ( ) ; / / Call EEPROM_STORE subroutine} Note:Only PROM byte 0-7 will be written back to EEPROM when ALL_STORE() is issued.
P/N: PM0365
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REV. 1.3, NOV 20 ,1995
MX98905B
9.6.1 7 IO BASES SUPPORTED 300H (18H ) -> 240H (22H) -> 280H (34H) -> 2C0H (46H) -> 320H (59H) -> 340H (64H) -> 360H (0BH) > 300H -> (18H) (CYCLIC) 9.6.2 15 IO BASES SUPPORTED 300H (18H) -> 240H (22H) -> 280H (34H) -> 2C0H (46H) -> 320H (59H) -> 340H (6AH) -> 360H (7BH) > 380H (8CH) ->3A0H (9DH) -> 3C0H (AEH) -> 3E0H (BFH) -> 200H (C0H) -> 220H (D1H) -> 2A0H E5H) > 2EH (07H) -> 300H (18H) (CYCLIC) 9.7 MULTIPLE CONFIGURATION LAN CARD AUTO By the way, when the guessed value is hit the Network I.D., a register call SIGNATURE (with value 78H, 'x') will be realeased by MX98905. If software can properly read the contents of SIGNATURE and ASR, then a conflit free IO base is found. If software can't access the value of SIGNATURE but ASR, then the guessed value is wrong. If software can't access the value of SIGNATURE nor ASR, then MX98905(s) is conflict with other add_on cards. In case SIGNATURE can be accessed by software, then user can write 1 to LOCKE bit of HCFR through port "NONCONFLICT_IOBASE+08H". The IO base of this LAN card will be locked all the time to prevent it from jumpping to other IO base when AUTO is issued. See application notes or call SE/FAE if you have any questions. To faciliate one to understand the "Mutiple LAN card auto configuration ", an example is shown below: (Follow the steps shown in application note) Condition : One LAN card with network ID 001111001001 : The second LAN card with network ID 0022220308 1. At the beginning, software first write AUTO. The IO base of both LAN card will be changed from their current IO bases to 300H. 2. Software guesses 00H, then write AUTO. Because the guessed I.D. (SID) hits the network I.D. on both LAN card, the IO bases of these two LAN cards will jump to 240H (assume software choose 7 IO bases) 3. Software guesses 01H, then issue AUTO. The software guessed I.D. (SID) hits the network I.D. (HID) of the first card, hence the IO base of the first card will stay at 240H and the IO base of the second card jumpped to 280H. Software can access "x" (78H,SIGNATURE register) from IO base 248H. 4. Software write 1 to LOCKE bit to lock the first card. 5. Software keep guessing and writing 1 to AUTO. Finally, a value, 08H, is guessed by software, and the IO base of card #2 jump to 240H. Because 240H is conflict with card #1, user can only access the value of ASR butSIGNATURE. 6. Software keep guessing and writing 1 to AUTO. The IO base of card #2 change from 240H to 280H. 7. User can access SIGNATURE and ASR from this IO base, the conflit_free IO base for card #2 is found. Note : MX98905 uses one byte (ID byte #5) to determine SID is matched with HID or not, therefore, there is 1/256 posibility for 2 LAN cards get hit simultaneously.
In case it is necessary for system to have more than one LAN cards plugged, the MX98905 provides a powerful solution to resolve "Multiple LAN card IO base conflict problem". It is not necessary for users to plug one LAN into the system then configure the IO base of the LAN card; then remove the first LAN card which is already configured and proceeds the second LAN card and so forth. Using MX98905, user can plug mutiple LAN cards into the system at the same time and then use software to configure these LAN cards for themselves. To simply the mutiple LAN card auto configuration's operation, the MX98905 provides a bit, MULTI, in the HCMR. When this bit is set to 1, all LAN cards which use MX98905 will be forced to change to IO map (i.e. Novell NE2000 compaible). The "ID guess state machine" inside the MX98905 will be enables after MULTI bit is enabled. After that, software can write a certain value (will be explained in more detail in the following sub_ section) into the MX98905 by consecutive 4 write to port 378H. The following shows an example (in 8088 assembly code) for writting this certain value into MX98905: mov dx, 378 mov al, CERTAIN_VALUER out dx, al out dx, al out dx,al out dx,al When this certain value "hits" the 5th Network I.D. (the least significant byte), then IO base of this "ID hit" LAN card will be locked by MX98905 itself. i.e when writting 1 to AUTO, the IO base will not be changed.
P/N: PM0365
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REV. 1.3, NOV 20 ,1995
MX98905B
The internal state machine will be reset after EEPROM_STORE is finished. This algorithm is preliminary. For actual implementation, user can contact with our FAE by calling 886-027191977 for details. When these conditions are satisfied a control signal will be generated to show the remainder of the circuitry that valid data is present. Then the smart squelch circuitry is reset. Valid data is deemed present until either squelch level has not been generated for a time longer than 150 ns, which shows End of Packet. If good data is detected, the squelch levels are reduced to contain the noise effect which may lead to premature Endof-Packet detection.
10. TWISTED-PAIR INTERFACE (TPI) MODULE The TPI has five main logical functions: 1. The Smart Squelch is responsible for determining when valid data is present on the differential receive inputs RXIP and RXIM 2. The Collision function checks for simultaneous transmission and reception of data on the TXOP, TXOM, RXIP and RXIM. 3. The Link Detector/Generator checks the integrity of the cable connecting the two twisted-pair MAUs. 4. The Jabber disables the transmitter if it attempts to transmit a longer-than-legal packet. 5. The TX Driver & Pre-emphasis transmit Manchester-encoded data to the twisted-pair network via the summing resistors and transformer/filter.
12. COLLISION A collision is detected by the TPI module when the receive and transmit channels are active simultaneously. If the TPI is receiving when a collision is detected it is reported to the controller immediately. If, however, the TPI is transmitting when a collision is detected the collision is not reported until seven bits have been received while in the collision state. This prevents a collision from being reported incorrectly due to noise on the network. The signal to the controller remains for the duration of the collision. Approximately 1ms after the transmission of each packet a signal called the Signal Quality Error (SQE) consisting of typically 10 cycles of 10 MHz is generated. This 10 MHz signal, also called the Heartbeat, ensures the continued functioning of the collision circuitry.
11. SMART SQUELCH To make sure that impulse noise on the receive inputs will not be mistaken for a valid signal, the ENC carries out an intelligent receive squelch on the RX differential inputs. The squelch circuitry uses a mix of amplitude and timing measurements. Smart squelch checks the signal at the start of packet and any pulses that do not exceed the squelch level, either positive or negative, depending on polarity, is rejected. After this first squelch level is overcome the opposite squelch level must be exceeded within 150 ns. Finally, the signal goes beyond the original squelch level within a further 150 ns in order for the input waveform not to be rejected. The procedure entails the loss of at least three bits at the start of each packet.
13. LINK DETECTOR/GENERATOR This is a timer circuit that generates a link pulse as shown in the 10BASE-T specification. With a width of 100 ns, the pulse is transmitted every 16 ms on the TXO+ output in the absence of transmit data. The pulse checks the integrity of the connection to the remote MAU, and the link detection circuit checks for valid pulses from the remote MAU. The link detector will disable the transmit, receive, and collision detection functions if valid link pulses are not received. To determine that a good twisted-pair link exists, the GDLNK output directly drives an LED; the LED will be on during normal conditions.
P/N: PM0365
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REV. 1.3, NOV 20 ,1995
MX98905B
14. JABBER Whenever the transmitter is active for greater than 52 ms, the jabber timer monitors the transmitter and disables the transmission. In this case, the transmitter is then disabled for the time that ENDEC module's internal transmit enable is asserted. This signal has to be deasserted for about 750 ms before the jabber re-enables the transmit outputs. seven consecutive link pulses or three consecutive link pulses having reversed polarity are detected. A wiring error at either end of the TPI cable can cause polarity reversal. Upon detection of this reversal the condition is latched and POL is asserted. Correcting this error is the TP1 and will also decode received data correctly, thus getting rid of the need to check the wiring error.
17. MANCHESTER ENCODER AND DIFFERENTIAL DRIVER 15. TRANSMIT DRIVER The transmitter has four signals, the true and complement Manchester-encoded data (TXOP and TXOM). These signals may be delayed by 50 ns (TXODP and TXODM). These four signals are combined, TXOP with TXODM and TXOM with TXODP. Known as digital pre-emphasis, this process is required to compensate for the twisted-pair cable which acts like a low-pass filter and can greatly weaken the 10 MHz (50 ns) pulses of the Manchester-encoded waveform than the 5 MHz (100 ns) pulses. A combination of these signals is shown below:
DATA PATTERN 1 1 0 0 1 1
On the transformer's secondary, the differential transmit pair drives up to 50 meters of twisted-pair AUI cable. These outputs are source followers requiring two 270W pulldown resistors to ground.
18. MANCHESTER DECODER This decoder is composed of a differential receiver and a PLL to separate a Manchester-decoded data stream into internal clocks signals and data. When using the standard 78W transceiver drop cable, see that the differential input must be externally terminated with two 39W resistors connected in series. These resistors are optional in Thin Ethernet applications. A squelch circuit at the input rejects signals with levels less than 175 mV to prevent noise from triggering the decoder. And signals negative than -300 mV are decoded; data becomes valid within 5 bit times. The MX98905 may be able to take bit jitter up to 18 ns in the data that is received.
TXOP
TXODM
19. COLLISION TRANSLATOR If the Ethernet transceiver, when in AUI mode, detects a collision, it generates a 10 MHz signal to the differential collision inputs (CDP and CDM) of the MX98905. When these inputs are active, the MX98905 uses this signal to cancel its current transmission and reschedule another one. The collision differential inputs are ended in the same way as the differential receive inputs. The squelch circuitry is also similar, rejecting pulses with levels less than -175 mV. 20. RECEIVE DESERIALIZER The receive deserializer starts to work when the input
COMBINED WAVEFORM WITH PRE-EMPHASIS
16. STATUS INFORMATION This information is shown at the ENC on the CRS/RX, TXE/TX, COL and POL outputs as decribed in the pin description table. These outputs can drive status LEDs by means of an appropriate driver circuit. Normally low, the POL output will be driven high when
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MX98905B
signal Carrier Sense is asserted. It allows incoming bits to be shifted into the shift register by the receive clock provided by the SNC (Serial Network Converter). The serial receive data is also routed to the CRC generator/checker to detect CRC code. The receive deserializer includes a synch detector that detects the SFD (Start of Frame Delimiter) to establish where byte boundaries within the serial bit stream are located, i.e., when a 1,1 bit sequence is detected, it begins to collect data. After every eight receive clocks, the byte-wide data is transferred to the 16-byte FIFO (two 8-byte FIFOs) alternatively and the receive byte count is incremented. The first six bytes after the SFD are checked for valid comparison by the Address Recognition Logic. If the address recognition Logic does not recognize the packet, the FIFO is cleared. addition, if transmitting data is smaller than 46 bytes, the packet must be padded to a minimum size of 64 bytes. The programmer is responsible for adding and stripping pad bytes.
GENERAL TRANSMIT PACKET FORMAT
PREAMBLE 62 BITS
SYNCH
2 BITS
DESTINATION ADDRESS
6 BYTES
SOURCE ADDRESS TX BYTE COUNT (TBCR 0, 1)
6 BYTES
TYPE LENGTH
2 BYTES
21. ADDRESS RECOGNITION LOGIC The address recognition logic compares the destination address field (first 6 bytes of the received packet) with the physical address registers stored in the address register array, one byte at a time, by the 8th receive clock. If any one of the six bytes does not match the pre-programmed physical address, the protocol PLA rejects the packet. This means that the packet does not belong to the node. All multicast destination addresses are filtered using a hashing technique by latching the 6 most significant bits of the CRC generator. If the multicast address indexes a bit that has been set in the filter bit array of the multicast address register array, the packet is accepted. Otherwise, it is rejected by the Protocol PLA. Each destination address is also checked for all 1's, which is the reserved broadcast address.
DATA PAD (IF DATA < 46 BYTES)
> 46 BYTES
CRC
4 BYTES
23. CONDITIONS REQUIRED TO BEGIN TRANSMISSION To initiate transmission of a packet, the TPSR (Transmit Page Start Register) and TBCR0, TBCR1 (Transmit Byte Count Registers) must be initialized and the TXP bit in the Command Register must be set. The ENC will start to prefetch transmit data from memory, if no reception is currently receiving. Three conditions must be met before transmission: 1. The Interframe Gap Timer has timed out the first 6.4ms of the Interframe Gap. 2. At least one byte has entered the FIFO, which means that burst transfer has begun. 3. If collision occurs in the ENC, the backoff timer must expire before retransmit. If carrier sense is asserted before a byte has been loaded into the FIFO, the ENC will become a receiver.
22. PACKET TRANSMISSION A complete transmit packet consists of Preamble, Synch, Data, and CRC fields. The data field is a contiguous assembled packet of Destination Address. Source Address, Length Field, and Data with the format are shown below. During transmit, Page Start Address Register (TPSR) and the Transmit Byte Count Registers (TBCR0,1), control the DMA transfer. As a transmit command is issued to ENC, the packet of data in buffer memory pointed 0 by these registers will be moved into the FIFO. The ENC will generate and append the preamble, synch and CRC fields. In
P/N: PM0365
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REV. 1.3, NOV 20 ,1995
MX98905B
24. COLLISION RECOVERY If transmission has collided with another station, the buffer management logic, which monitors the transmit circuitry will reset the FIFO and restore the Transmit DMA pointers for retransmission of the packet. When collision is detected, the COL bit in TSR will be set and the NCR (Number of Collisions Register) will be incremented. If each of the 15 retransmissions results in a collision, the transmission will be terminated and the ABT bit in the TSR will be set. If excessive collisions (i.e., 16 consecutive collisions) are encountered, NCR reads as zeros and transmission is aborted. BOS = 0, WTS -1 in Data Configuration Register. This format used with Series 32000, 808X-type processors.
BIT D15 D8 D7 D0
DA0
DA1
DA2
DA3
DA4
DA5
SA0
SA1
SA2
SA3
25. TRANSMIT PACKET ASSEMBLY FORMAT
SA4 SA5
The following diagrams show the format for assembling packets before they are transmitted for different byte- ordering schemes. The various formats are selected in the Data Configuration Register. DA = Destination Address SA = Source Address T/L = Type/Length Field
T/L0
T/L1
DATA0
DATA1
BOS = 1, WTS = 1 in Data Configuration Register. This format is used with 68000-type processors.
D8 D7 D0
BIT
D15 DA1
DA0
DA3
DA2
DA5
DA4
SA1
SA0
SA3
SA2
SA5
SA6
T/T1
T/L0
DATA1
DATA0
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MX98905B
DA0
DA1
DA2
DA3
DA4
DA5
SA0
SA1
SA2
SA3
BOS = 0, WTS = 1 in data Configuration Register. This format is used with general 8-bit CPUs.
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MX98905B
26. PHYSICAL ADDRESS REGISTERS (PAR0PAR5) The physical address registers are used to compare the destination address of incoming packets for rejecting or accepting packets. It compares physical addresses in PAR0-PAR5 with incoming data one byte at a time. The bit assignment shown below relates the sequence in PAR0-PAR5 to the bit sequence of the received packet.
D7 PAR0 PAR1 PAR2 PAR3 PAR4 PAR5 DA7 DA15 DA23 DA31 DA39 DA47
D6 DA6 DA14 DA22 DA30 DA38 DA46
D5 DA5 DA13 DA21 DA29 DA37 DA45
D4 DA4 DA12 DA20 DA28 DA36 DA44
D3 DA3 DA11 DA19 DA27 DA35 DA43
D2 DA2 DA10 DA18 DA26 DA34 DA42
D1 DA1 DA9 DA17 DA25 DA33 DA41
D0 DA0 DA8 DA16 DA24 DA32 DA40
DESTINATION ADDRESS P/S DA0 DA1 DA2 DA3 .......... DA46 DA47
SOURCE SA0 ..........
NOTE: P/S = Preamble, Synch DA0 = Physical/Multicast Bit
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MX98905B
REGISTER ADDRESS MAPPING
COMMAND REGISTER
ADDRESS DECODE PS1, PS0 COMMAND COMMAND
PAGE 0 (READ) SWR# SRD# CS# RA0-RA3 PAGE 1 (READ) COMMAND
PAGE 0 (WRITE)
COMMAND
PAGE 1 (WRITE)
COMMAND
COMMAND
PAGE 2 (READ)
PAGE 2 (WRITE)
COMMAND
COMMAND
TEST PAGE
TEST PAGE
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MX98905B
27. DIRECT MEMORY ACCESS CONTROL (DMA) The DMA capabilities of the ENC greatly simplify use of the MX98905 in typical configuration. The local DMA channel transfers data between FIFO, which is inside the ENC, and memory which is outside the ENC. There are two kinds of local DMA type: Local DMA Read and Local DMA Write. Local DMA Read moves data from memory into FIFO on transmission. Should a collision occur (up to 15 times), the packet is retransmitted with no processor intervention. Local DMA Write transfers data from FIFO to memory on reception. A remote DMA channel is also provided on the ENC to accomplish transfers between a buffer memory and a system memory whenever the I/O map board design is required. The two DMA channels (local DMA and remote DMA) can alternatively be combined to form a single 32-bit address with 8- or 16-bit data.
28. DUAL DMA CONFIGURATION Network activity is isolated on a local bus, where the ENC's local DMA channel performs burst transfers between the buffer ring and the ENC's FIFO. The remote DMA transfers data between the buffer ring and the host memory by means of a bi-directional I/O port. Meanwhile, remote DMA provides local addressing capability and is used as a slave DMA by the host. Host side addressing must be provided by a host DMA or the CPU. The ENC allows Local and Remote DMA operations to be interleaved because the ENC takes care of the bus arbitration problem itself.
29. INTERNAL REGISTERS All internal registers are mapped into three pages and selected by two bits, PS1 and PS0, of Command Register. Input pins RA0-RA3 are used to address these internal registers which are 8-bit wide and are commonly accessed during ENC register read/write operation. For user's convenience, registers that are commonly accessed during ENC operation are mapped into page 0. Page 1 registers are used primarily for initialization while Page 2 registers are used for diagnostics. Partitioned registers make one write/read cycle possible for accessing those commonly used registers.
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REGISTER DESCRIPTIONS
1. ENHANCED FEATURE NEW PAGE REGISTER ADDRESS ASSIGNMENT
NEW PAGE 1 ADDRESS ASSIGNMENT FOR I/O MAP SA00..3 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH READ Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Signature (x, 78H) Hidden Config. (HCFR) Hidden Command (HCMR) Reserved Configuration C (CC) Reserved AutoStatus Reg. (ASR) Reserved WRITE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Hidden Config. (HCFR) Hidden Command (HCMR) Reserved Configuration C (CC) Reserved Reserved Reserved
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NEW PAGE 1 ADDRESS ASSIGNMENT FOR MEMORY MAP SA0..4 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH READ Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Signature (x, 78H) Hidden Config. (HCFR) Hidden Command (HCMR) Reserved Configuration C (CC) Reserved AutoStatus Reg. (ASR) Reserved WRITE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Hidden Config. (HCFR) Hidden Command (HCMR) Reserved Configuration C (CC) Reserved Reserved Reserved
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Data Transfer ports and Reset port are always accessible no matter what the value of NPGEN and PGSEL is in I/O map design.
2. ENHANCED FEATURE REGISTERS 2.1 HIDDEN COMMAND REGISTER (R/W) (HCMR) This register controls all the functions provided in enhanced mode. It can always be accessed by consecutive 2 writes to port 278H, followed by 2 consecutive 2 writes to port 378H, i.e., write ports : 278H AE 278H AE 378H AE 378H (when I/O Base not sure) After the I/O base is determined (see functional description), this register can be accessed by one I/O instruction using the address assignment shown in provious section.
NOTE: Don't write this register through Base+0AH/ Base+1AH (I/O/MEM) except it is confirmed that I/O base does not conflict with other ADD_on card.
Bits
7
6
5
4
3
2
1
0
HCFRE PGSEL NPGEN AUTO IDWCMD ALLWR MULTI RESVD
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MX98905B
HIDDEN COMMAND REGISTER (R/W) (HCMR)
SYMBOL HCFRE BIT D0 DESCRIPTION Register HCFRE Enable. Power on low. 0 : Disable HCFR. 1 : Enable HCFR. When user issues EESTORE in Configuration Register B, contents in figh byte of OFH of EEPROM. Whcih is reserved at New Page Enable/Page Select. Power on low. 0X: Normal Mode. User can access controller's internal registers. 10 : User can access IDPROM through IOBASE + 00..OFH in I/O map. See table 4 for your reference. 11: New Page 1 selectsd. User can access HCMR, CC, ASR and SIGNATURE. See "New Page 1 address assignment for I/O map" and "New Page 1 address assignment for Memory map " for more detail information. Make sure set NPGEN to 0 before normal operation. Data port and Reset port in I/O map are accessible no matter what the value of NPGEN and PGSEL are. Auto Jump to Next I/O base. Power on low. 0 : Write a 0 to this bit has no effect.1 : Write an 1 to this bit will cause I/O base auto jump follow the sequence described in section 9.5- - Auto Configuration. In multiple LAN cards auto configuration's application (see section 9.5), if SID hits the HID, then write an 1 to this bit has no effect. The first time writing an 1 to AUTO will cause IO base change to 300H no matter what the current IO base is. Whenever AUTO is issued, the value of IOAD2..0 in CA and PAGE in HCFR will be updated automatically by the state machine inside the MX98905. Either 7 or 15 IO bases should be determined before AUTO is issued to prevent the internal state machine getting confused. Any IORDL signal activates will reset this bit. IDPROM Write Command. Power on low. 0 : Write a 0 to this bit has no effect. 1 : The MX98905 will write the first 4 words of PROM data (Net work I.D., Boardtype and Checksum) back to EEPROM when this bit is set. When the operation is completed, this bit will be reset by MX98905 itself. Don't write an 1 to this bit and EESTORE of CB simultaneously, this will cause internal state machine malfunction. Write CA, CB, CC, HCFR, The entire PROM content back to EEPROM. Power on low. 0 : Only CA, CB, CC and HCFR are written back to EEPROM when EESTORE bit of CB is set to 1. 1 : CA, CB, CC, HCFR, and the entire PROM content will be writtenback to EEPROM when EESTORE bit is set to 1. If new Network I.D. is necessary, make sure I.D. is updated before this bit-is set and before EESTORE bit is set to1, the following write sequence will be followed after EESTORE bit is set to 1, CA, CB -> CC, HCFR -> IDO, IDI -> ID2, ID3 -> ID4, ID5 -> and the rest of the content in PROM.
REV. 1.3, NOV 20 ,1995
NPGEN,PGSEL
D2,D1
AUTO
D3
IDWCMD
D4
ALLWR
D5
P/N: PM0365
36
MX98905B
HIDDEN COMMAND REGISTER (R/W) (HCMR)(Continued)
SYMBOL MULTI BIT D6 DESCRIPTION Enable Multiple LAN card Auto Configuration 0 : Disable consecutive 4 writes to port 378H (SID buffer) . 1 : The MX98905 will be forced to I/O map, i.e. MEMIO of CA will be forced to zero. Consecutive 4 writes to port 378H will be enabled. When a 0 is written to this bit, the MX98905 will change to its original mode (I/O or memory). Reserved. Power on low.
RESVD
D7
Note : HCMR can always be accessed by writing to port 278H and 378H(follow the certain sequence described above). Remember not to access this register through direct IO access unitl a conflict _free I/O base is found.
2.2 HIDDEN CONFIGURATION REGISTER (R/W) (HCFR) This register controls all the functions provided in enhanced mode. It can always be accessed by consecutive 2 writes to port 278H, followed by 2 consecutive 2 writes to port 378H, i.e., write ports : 278H AE 278H AE 378H AE 378H (when I/O Base not sure) After the I/O base is determined (see functional description), this register can be accessed by one I/O instruction using the address assignment shown in provious section.
NOTE: Don't write this register through Base+0AH/ Base+1AH (I/O/MEM) except it is confirmed that I/O base does not conflict with other ADD_on card.
Bits
7 x
6 x
5 x
4 x
3
2
1
0
IOBEN PAGE NEWCF LOCKE
P/N: PM0365
37
REV. 1.3, NOV 20 ,1995
MX98905B
2.2 HIDDEN CONFIGURATION REGISTER (R/W) (HCFR)(Continued)
SYMBOL IOBEN BIT D0 DESCRIPTION I/O BASE ENABLE. Power-on low 0 : 7 I/O base (compatible with DP83905) 1 : 15 I/O bases PAGE D1 PAGE SELECT FOR I/O BASE. Power-on low only valid when IOBEN and HCFRE of HCMR is high 0 : I/O base address are the same as IOAD2..0 of Configuration A 1 : I/O base address are redefined (see I/O Base support for more detail). This bit will be updated automatically according to the sequence of AUTO configuration when IOBEN is set. NEWCF D2 NEW CONFIGURATION LOADED TO CA, CB AND CC AFTER EESTORE IS EXECUTED. Power-on low 0 : New configuration will not be loaded to CA, CB and CC after EESTORE algorithm is executed. Compatible with DP83905. 1 : New Configuration will be loaded to CA, CB and CC after EESTORE algorithm is completed. Enhanced feature. LOCKE D3 LOCK ENABLE. I/O base will not be changed when AUTO of HCMR is written into. Power-on low. 0 : Enable internal LOCK bit. Write 1 to AUTO will change I/O base 1 : Enable internal LOCK bit. Write 1 to AUTO will not change I/O base. When this bit is set, AUTO of HCMR has no effect. User CANNOT read the value of Signature Register. After I/O base is determined (see Multi_lan card conflict free for more detail), this bit should be programmed through base+09H for I/O map or Base+19H for shared memory map.
These four bits (IOBEN, PAGE, NEWCF and LOCKE) can be loaded/stored from/to EEPROM. RESV4..1 --- Reserved bits for future use.
Note: Don't write this register through Base+09H/ Base+19H except it is confirmed that I/O Base does not conflict with other Add_on card.
P/N: PM0365
38
REV. 1.3, NOV 20 ,1995
MX98905B
2.3 SIGNATURE FOR MULTI_BOARD AUTO CONFIGURATION (R) (SGN) This register is only used in multi_LAN card auto configuration. It is readable only when the LSB of Network ID programmed by user is matched with the contents of ID5 of PROM. * Read port : Base + 08H/Base + 18H (I/O/ MEM) * Read condition NPGEN = 1 PGSEL = 1 * The value of signature is 78H (ASCII code for 'x')
Bits
7
6
5
4
3
2
1
0
IOB5 IOB6 IOB7 IOB8 AUTY0 AUTY1 AUTY2 AUTY3
Note : Lock status will be reset after user has read the value of signature. User should exactly follow the algorithm provided in enhanced feature description for Multi_board Lan Card auto configuration. For user's convenience, we strongly recommend that he issues EESTORE after auto configuration is done.
IOB8..5 : I/O base bit 8 to bit 5. AUTY3..0 : States for Auto configuration state machine.
2.5 AUTOSTATUS REGISTER (R) (ASR) * Read port : Base + 0EH/Base + 1EH (I/O/ MEM) * Read condition : NPGEN = 1 PGSEL = 1 When 7 I/O bases are selected, the following value sequence will be shown on ASR whenever AUTO of HCMR is written into: 18 AE 22 AE 34 AE 46 AE 59 AE 6A AE 0B When 15 I/O bases are enabled, the following sequence is available: 18 AE 22 AE 34 AE 46 AE 59 AE 6A AE 7B AE 8C AE 9D AE AE AE BF AE C0 AE D1 AE E5 AE 07 i.e., when AUTO is first written, the contents of ASR are 18H; if user writes AUTO again, the value of ASR changes from 18H to 22H, etc. This feature can be used in auto configuration to determine whether the I/ O base of the LAN card is in conflict with the others.
P/N: PM0365
39
REV. 1.3, NOV 20 ,1995
MX98905B
3. CONFIGURATION REGISTERS 3.1 CONFIGURATION REGISTER A (R/W) (CA) This register can be accessed by reading 0AH of internal page 0 register followed by writing to that address. If other Read/Write takes place between the read and the write, then write to 0AH will access the Remote Byte Count Register 0.
Bits
7
6
5
4
3
2
1
0
IOAD0 IODA1 IOAD2 INT0 INT1 INT2 FREAD MEMIO
SYMBOL IOAD2-0
BIT D0-D2
DESCRIPTION I/O ADDRESS. These three bits determine the base I/O address of the MX98905 controller when enhanced mode is disabled (NPGEN of HCMR is low). When the enhanced mode is enabled, the base I/O address will be determined by 5 bits, which are IOAD2-0 of CA, NPGEN and PGSEL of HCMR. See I/O base determination for details. INTERRUPT LINE USED. Two interrupt modes are supported by the MX98905, which can be enabled by setting INTMOD of Configuration C. Direct Drive Mode : In this mode, an interupt output pin will be driven active on a valid interrupt condition (see ISR for more detail). Only one pin is driven in this mode depending on the following condition, the other three will remain TRI-STATE. INT2 X X X X INT1 0 0 1 1 INT0 0 1 0 1 INTERUPT INT0 INT1 INT2 INT3
INT2-0
D3-D5
Code Output Mode : INT3 is the active interrupt output while pins INT0-INT2 are programmable outputs reflecting the values on bits 3 to 5, i.e., when bits 3 and 4 of CA is high, then INT0, INT1 and INT3 are driven.
P/N: PM0365
40
REV. 1.3, NOV 20 ,1995
MX98905B
3.1 CONFIGURATION REGISTERS A (R/W) (CA) (Continued)
SYMBOL FREAD BIT D6 DESCRIPTION FAST READ. When this bit is set, the MX98905, in I/O mode, will begin next port fetch before system finishes reading the current data in data port. In slow ISA system, programming this bit may cause data corrupt in data port. MEMORY OR I/O MODE. When this bit is set to 0, I/O mode is selected. When it is set high, it is in shared memory mode.
MEMIO
D7
P/N: PM0365
41
REV. 1.3, NOV 20 ,1995
MX98905B
3.2 CONFIGURATION REGISTER B (R/W) (CB) This register can be accessed by reading 0BH of internal page 0 register followed by writing to that address. If other Read/Write takes place between the read and the write, then write to 0BH will access the Remote Byte Count Register 1. When loading from EEPROM during power-on reset, note that the value of EESTORE is always 0, i.e., the value of EESTORE can only be changed during Register Write operation.
Bits
7
6
5
4
3
2
1
0
PHYS0 PHYS1 GDLINK IO16CON CHANRDY BE BPWR EESTRORE
SYMBOL PHYS0-1
BIT D0-D1
DESCRIPTION PHYSICAL LAYER INTERFACE. PHYS1 0 0 1 1 PHYS0 0 1 0 1 INTERFADCE TPI (10BASE-T compatible Squelch Level) Thin Ethernet (10BASE2, THIN pin high) Thick Ethernet (10BASE5, AUI port) TPI (Reduced Squelch Level)
The THIN pin can be used to enable the DC-DC converter required by 10BASE2 specification to provide electrical isolation. GDLINK D2 GOOD LINK. There are different definitions for this bit in Write and Read modes. Write Mode : Write 1 to this bit will disable the link pulse integrity test. Read Mode : When this bit is read, it indicates the link status, reflecting the value shown on the GDLINKL LED. 0 : A. B. 1 : A. B. The MX98905 is in AUI mode The MX98905 is in TPI mode, link enable, link bad Link disable The MX98905 is in TPI mode, link enable, link good
P/N: PM0365
42
REV. 1.3, NOV 20 ,1995
MX98905B
31 CONFIGURATION REGISTER B (R/W) (CB) (Continued)
SYMBOL IO16CON BIT D3 DESCRIPTION IO16L CONTROL. When this bit is set low, IO16L is generated only on address decode. When it is high, the MX98905 will generate IO16L after IORDL, or IOWRL go active. CHRDY FROM IORDL OR IOWRL OR FROM BALE. When this bit is set low, the MX98905 will generate CHRDY after the command strobe. When it is high, CHRDY will be generated by the MX98905 after BALE goes high. BUS ERROR. This bit shows that the MX98905 has detected a bus error (the MX98905 attempts to insert wait state into a system access and the system terminates the cycle without monitoring the wait state). Writing a one to this bit clears it to zero, but writing a zero to this bit has no effect. BOOT PROM WRITE. Write cycles will be generated to the boot PROM only when this bit is set high. EEPROM STORE. Writing a one to this bit enables the EEPROM STORE algorithm, as mentioned. This bit should not be configured to high either from switches or from an EEPROM. Note that this bit and IDWCMD of HCMR can't be set high simultaneously to prevent crashing the internal state machine of the MX98905.
CHANRD
D4
BE
D5
BPWR
D6
EESTORE
D7
P/N: PM0365
43
REV. 1.3, NOV 20 ,1995
MX98905B
3.3 HARDWARE CONFIGURATION REGISTER C (CC) Access to Configuration Register C is allowed only in the MX98905 enhanced mode. This feature is not supported when the MX98905 is not programmed to new page 1. * * Read/write port : Base + 0CH/Base + 1CH (I/O/MEM) Read/write condition: NPGEN = 1 PGSEL = 1
Bits 7 6 5 4 3 2 1 0
BPS0 BPS1 BPS2 BPS3 COMP INTMOD CLKSEL SOFEN
SYMBOL BPS0-3
BIT D0-D3
DESCRIPTION BOOT PROM SELECT. Selects address and the size with which boot PROM begins. When the system reads within the selected memory area, the MX98905 reads the data in through MEMD0-7 and drives it onto the system data bus. The following are valid addresses and size provided by the MX98905: BPS3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BPS2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BPS1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BPS0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ADDRESS X 0C000H 0C400H 0C800H 0CC00H 0D000H 0D400H 0D800H 0DC00H 0C000H 0C800H 0D000H 0D800H 0C000H 0D000H SIZE (I/O SHARED MEMORY) No boot prom 8K/16K 8K/16K 8K/16K 8K/16K 8K/16K 8K/16K 8K/16K 8K/16K 32K/32K 32K/32K 32K/32K 32K/32K 64K/64K 64K/64K
P/N: PM0365
44
REV. 1.3, NOV 20 ,1995
MX98905B
3.3 HARDWARE CONFIGURATION REGISTER C (CC) (Continued)
SYMBOL COMP BIT D4 DESCRIPTION COMPATIBLE. When this bit is low, the MX98905 is compatible with the EtherCard PLUS and Novell NE2000 boards. In compatible mode, only 16 kbytes RAM memory are accessible. When this bit is set high, full 64 kbytes of memory can be accessed. INTERRUPT MODE. When this bit is low, the MX98905 is in Direct Drive Interrupt mode. When it is high, Coded Output interrupt mode is selected. CLOCK SELECT. If this bit is high, the MX9890 core is clocked by the input BSCLK pin. If it is low, the MX9890 core is clocked by the 20MHz clock from internal MCC module. SOFTWARE ENABLE. 0 : User can program Configuration Register A and B in software. 1 : CA and CB are not accessible.
INTMOD
D5
CLKSEL
D6
SOFEN
D7
P/N: PM0365
45
REV. 1.3, NOV 20 ,1995
MX98905B
4. SHARED MEMORY MODE CONTROL REGISTERS 4.1 SHARED MEMORY AT DETECT REGSITER (R)
Bits
7 X
6 X
5 X
R X
3 X
2 X
1 X
0
ATDET
SYMBOL ATDET
BIT D0
DESCRIPTION AT DETECT. This bit shows the value on the ATXT pin and can be accessed by software to determine whether the MX98905 is operating in an 8- or 16-bit slot. When this bit is high, the MX98905 is operating in a 16-bit slot.
P/N: PM0365
46
REV. 1.3, NOV 20 ,1995
MX98905B
4.2 SHARED MEMORY CONTROL REGISTER 1 (C1)
Bits
7
6
5
4
3
2
1
0
A13 A14 A15 A16 A17 A18 MEME RESET
SYMBOL A13-18
BIT D0-D5
DESCRIPTION A13 TO A18. Lower part of the address register used to determine the position of the memory of the MX98905 within the system memory map. MEMORY ENABLE. Enables external memory accesses when held high. Poweron low. To enable the memory into the system's memory map, the user must program the base memory address and set this bit high. RESETS. Resets the MX9890 core of the MX98905 controller.
MEME
D6
RESET
D7
P/N: PM0365
47
REV. 1.3, NOV 20 ,1995
MX98905B
4.3 SHARED MEMORY CONTROL REGISTER 2 (C2)
Bits
7
6
5
4
3
2
1
0
LA23 LA23 LA23 LA23 LA23 UNUSED MEMW EN16
SYMBOL LA19-23
BIT D0-D4
DESCRIPTION LA19 TO LA23. Upper part of the address register used to determine the position of the memory of the MX98905 within the system memory map. MEMORY WIDTH. Sets width of external memory. When this bit is set high, external memory is accessed as word wide, i.e., in compatible mode, 16 kbytes are available and 64 kbytes are available in noncompatible mode (only when EN16 is set high also). When it is low, external memory is accessed as byte wide, so only 8 kbytes of memory are available in compatible mode and 32 kbytes of memory are available in noncompatible mode. ENABLE 16 BIT. Allow 16-bit system accesses to external memory when it is high. M16L output will be generated in this mode. When low, only 8-bit accesses are allowed, and M16L will stay high.
MEMW
D6
EN16
D7
P/N: PM0365
48
REV. 1.3, NOV 20 ,1995
MX98905B
5. COMMAND REGISTER(CR) 00H (READ/WRITE) The Command Register is used to take the controller on/ offline (STA and STP bits), initiate transmissions (TXP bit), enable or disable Remote DMA operations (RD2, RD1 and RD0 bits), and select register pages (PS1 and PS0). To issue a command, the microprocessor sets the corresponding bit(s). In addition, commands may be overlapped following the guidelines below: 1. If a remote DMA operation overlaps a transmission, RD0, RD1 and RD2 must be written with the desired values, and a "0" or "1" may be written to the TXP bit, because writing a "0" to TXP has no effect after transmission is activated. 2. A remote write DMA may not overlap remote read operation and vice versa. Each operation must either be completed or aborted before starting the other one. 3. If a transmit command overlaps with a remote DMA operation, bits RD2, RD1 and RD0 must be maintained for the remote DMA command when setting the TXP bit. NOTE: If a remote DMA command is reissued while giving the transmit command, the DMA will complete the process immediately if the remote byte count registers (RBCR1 and RBCR0) have not been reinitialized, i.e., user has to program RBCR0 and/or RBCR1 every time he needs remote DMA service. 4. Bits PS1, PS0, RD2 and STP can be set at any moment.
Bits
7
6
5
4
3
2
1
0
STP STA TXP RD0 RD1 RD2 PS0 PS1
P/N: PM0365
49
REV. 1.3, NOV 20 ,1995
MX98905B
5. COMMAND REGISTERS (Continued)
SYMBOL STP BIT D0 DESCRIPTION STOP: Software reset command, takes the controller offline; no Packets will be received or transmitted if this bit is set high. Any reception or transmission in progress will enter the reset state after operation is completed. This bit must be cleared and the STA bit must be set high to exit the reset state. The software reset is executed only when the RST bit in the ISR is set to 1. STP powers up high. Note: If the ENC has previously been in start mode and the STP is set, both the STP and STA bits will remain set. START: This bit is used to activate the ENC after either power-up, or when the ENC has been placed in a reset mode by software command or error. STA powers up low. TRANSMIT PACKET: This bit must be set to initiate transmission of a packet only after the Transmit Byte Count (TBCR1 and TBCR0) and Transmit Page Start register (TPSR) have been programmed. TXP is internally reset either after the transmission is completed or aborted. REMOTE DMA COMMAND: These three-encoded bits control operation of the Remote DMA channel. RD2 can be set to abort any Remote DMA command in progress. The Remote Byte Count Registers should be cleared by host whenever a Remote DMA has been aborted. The Remote Start Addresses are not restored to the starting address if the Remote DMA is aborted. Hence, for another remote DMA operaton, host should provide a starting address for ENC in order to operate correctly. RD2 0 0 0 0 1 PS0, PS1 D6, D7 RD1 0 0 1 1 X RD0 0 1 0 1 X
STA
D1
TXP
D2
PD0, PD1, PD2
D3, D4, D5
Not Allowed Remote Read Remote Write Send Packet Abort/Complete Remote DMA (Note)
PAGE SELECT: These two-encoded bits select which register page is to be accessed with addresses RA0-3 PS1 0 0 1 1 PS0 0 1 0 1
Register Page 0 Register Page 1 Register Page 2 Reserved
P/N: PM0365
50
REV. 1.3, NOV 20 ,1995
MX98905B
6. INTERRUPT STATUS REGISTER (ISR) 07H (READ/WRITE) This register is accessed by the host processor to determine the cause of an interrupt. Any interrupt can be masked in the Interrupt Mask Register (IMR). Individual interrupt bits are cleared by writing a "1" into the corresponding bit of the ISR. The INT signal is active as long as any unmasked signal is set; it will not go low until all unmasked bits in this register have been cleared. The ISR must be cleared after power-up by writing it with all 1's.
Bits
7
6
5
4
3
2
1
0
PRX PTX RXE TXE OVW CNT RDC RST
SYMBOL PRX PTX RXE
BIT D0 D1 D2
DESCRIPTION PACKET RECEIVED: Indicates packet received with no errors. PACKET TRANSMITTED: Indicates packet transmitted with no errors. RECEIVE ERROR: Indicates that a packet was received with one or more of the following errors: CRC Error Frame Alignment Error FIFO Overrun Missed Packet
TXE
D3
TRANSMIT ERROR: Set when packet is transmitted with one or more of the following errors: - Excessive Collisions - FIFO Underrun
OVW
D4
OVERWRITE WARNING: Set when receive buffer ring storage resources have been exhausted. (Current Pointer has reached Boundary Pointer)
P/N: PM0365
51
REV. 1.3, NOV 20 ,1995
MX98905B
6. INTERRUPT STATUS REGISTER (ISR) 07H (READ/WRITE) (Continued)
SYMBOL CNT BIT D5 DESCRIPTION COUNTER OVERFLOW: Set when MSB of one or more of the Network Tally Counters has been set. REMOTE DMA COMPLETE: Set when Remote DMA operation has been completed. RESET STATUS: Set when ENC enters reset state and cleared when a start command is issued to the CR. This bit is also set when a Receive Buffer Ring overflow occurs and is cleared when one or more packets has been removed from the ring. Writing to this bit has no effect. Note: This bit does not generate any interrupt; it is merely a status indicator.
RDC RST
D6 D7
7. INTERRRUPT MASK REGISTER (IMR) 0FH (WRITE) The Interrupt Mask Register is used to mask interrupts. Each interrupt mask bit corresponds to a bit in the Interrupt Status Register (ISR). If an interrupt mask bit is set, an interrupt will be issued whenever the corresponding bit in the ISR is set. If any bit in the IMR is set low, an interrupt will not occur when the bit in the ISR is set. The IMR powers up all zeros.
Bits
7 x
6
5
4
3
2
1
0
PRXE PTXE RXEE TXEE OVWE CNTE RDCE
P/N: PM0365
52
REV. 1.3, NOV 20 ,1995
MX98905B
7. INTERRUPT MASK REGISTER (IMR) 0FH (WRITE) (Continued)
SYMBOL PRXE BIT D0 DESCRIPTION PACKET RECEIVED INTERRUPT ENABLE 0: Disables Interrupt when packet is received. 1: Enables Interrupt when packet is received. PTXE D1 PACKET TRANSMITTED INTERRUPT ENABLE 0: Disables Interrupt when packet is transmitted. 1: Enables Interrupt when packet is transmitted. RXEE D2 RECEIVE ERROR INTERRUPT ENABLE 0: Disables Interrupt when packet is received with error. 1: Enables Interrupt when packet is received with error. TXEE D3 TRANSMIT ERROR INTERRUPT ENABLE 0: Disables Interrupt when packet transmission results in error. 1: Enables Interrupt when packet transmission results in error. OVWE D4 OVERWRITE WARNING INTERRUPT ENABLE 0: Disables Interrupt when Buffer Management Logic lacks sufficient buffers to store an incoming packet. 1: Enables Interrupt when Buffer Management Logic lacks sufficient buffers to store an incoming packet. CNTE D5 COUNTER OVERFLOW INTERRUPT ENABLE 0: Disables Interrupt when MSB of one or more of the Network Statistics Counters has been set. 1: Enables Interrupt when MSB of one or more of the Network Statistics Counters has been set. RDCE D6 DMA COMPLETE INTERRUPT ENABLE 0: Disables Interrupt when Remote DMA transfer has been completed. 1: Enables Interrupt when Remote DMA transfer has been completed. RESERVED D7 Reserved
P/N: PM0365
53
REV. 1.3, NOV 20 ,1995
MX98905B
8. DATA CONFIGURATION REGISTER (DCR) 0EH (WRITE) This register is used to program the ENC for 8- or 16-bit memory interface, select normal or loopback operation, select byte ordering in 16-bit application, and establish FIFO threshold. The DCR must be initialized prior to loading the Remote Byte Count Registers. LAS is set on power-up.
Bits
7 x
6
5
4
3
2
1
0
WTS BOS LAS LS ARM FT0 FT1
SYMBOL WTS
BIT D0
DESCRIPTION WORD TRANSFER SELECT 0: Selects byte-wide DMA transfers 1: Selects word-wide DMA transfers WTS establishes byte or word transfer for both Remote and Local DMA transfers. Note: When word-wide mode is selected, up to 32K words are addressable; A0 remains low.
BOS
D1
BYTE ORDER SELECT 0: MS byte placed on AD15-AD8 and LS byte on AD7-AD0 (32000, 8086) 1: MS byte placed on AD7-AD0 and LS byte on AD15-AD8 (68000); ignored when WTS is low.
LAS
D2
LONG ADDRESS SELECT 0: Dual 16-bit DMA mode 1: Single 32-bit DMA mode When LAS is high, the contents of the Remote DMA Registers RSAR0, 1 are issued as A16-A31. Power-up high.
P/N: PM0365
54
REV. 1.3, NOV 20 ,1995
MX98905B
9. DATA CONFIGURATION REGISTER (DCR) 0EH (WRITE) (Continued)
SYMBOL LS BIT D3 DESCRIPTION LOOPBACK SELECT 0: Loopback mode select. Bits LB0, LB1 o f the TCR must be programmed for loopback operation. 1: Normal Operation. Ignore the values of LB1 and LB0 of TCR. ARM D4 AUTO-INITIALIZE REMOTE 0: Send Command not executed, all packets removed from Buffer Ring under program control. 1: Send Command executed, Remote DMA auto-initialize to remove packets from Buffer Ring Note: Send Command cannot be used with 68000-type processors and should be issued right after reception of packet is completed. FT0, FT1 D5,D6 FIFO THRESHOLD SELECT: Encoded FIFO threshold; establishes point at which bus is requested when filling or emptying the FIFO. During reception, the FIFO threshold indicates the number of bytes (or words) the FIFO has filled serially from the network. During transmission, the FIFO threshold indicates the number of bytes (or words ) the FIFO has filled from the Local DMA. Thus, the transmission threshold is 16 bytes less than the received threshold. Note: FIFO threshold setting determines the Local DMA burst length. RECEIVE THRESHOLDS FT1 0 0 1 1 FT0 0 1 0 1 WORD WIDE 1 word 2 words 4 words 6 words BYTE WIDE 2 bytes 4 bytes 8 bytes 12 bytes
P/N: PM0365
55
REV. 1.3, NOV 20 ,1995
MX98905B
10. TRANSMIT CONFIGURATION REGISTER (TCR) 0DH (WRITE) Before transmission of a packet on the network, the Transmit Configuration Register is configured to establish the actions of the transmitter section of the ENC during transmission of a packet on the network. LB1 and LB0 select loopback mode power-up as 0.
Bits
7 x
6 x
5 x
4
3
2
1
0
CRC LB0 LB1 ATD OFST
SYMBOL CRC
BIT D0
DESCRIPTION INHIBIT CRC 0: CRC appended by transmitter 1: CRC inhibited by transmitter In loopback mode CRC can be enabled or disabled to test the CRC logic.
LB0, LB1
D1, D2
ENCODED LOOPBACK CONTROL: The type of loopback to be performed is determined by the following encoded bits. LB1 0 0 1 1 LB2 0 1 0 1
Mode Mode Mode Mode ATD D3
0 1 2 3
Normal Operation Internal Loopback External Loopback to SNI External Loopback to TP
AUTO TRANSMIT DISABLE: Setting this bit allows another station to disable the ENC's transmitter by transmission of a particular multicast packet. The transmitter can be re-enabled by resetting this bit, or by reception of a second particular multicast packet. 0: Normal Operation 1: Reception of multicast address hashing to bit 62 disables transmitter; reception of multicast address hashing to bit 63 enables transmitter.
P/N: PM0365
56
REV. 1.3, NOV 20 ,1995
MX98905B
11 TRANSMIT CONFIGURATION REGISTER (TCR) 0DH (WRITE) (Continued)
SYMBOL OFST BIT D4 DESCRIPTION COLLISION OFFSET ENABLE: This bit modifies the backoff algorithm to allow prioritization of modes. 0: Normal Backoff algorithm 1: Forces Backoff algorithm modification to 0 to 2 min (3+n, 10) slot times for first three collisions, then follows standard backoff.( For first three collisions station has higher average backoff delay making a low-priority mode.) RESERVED RESERVED RESERVED D5 D6 D7 Reserved Reserved Reserved
12. TRANSMIT STATUS REGISTER (TSR) (READ)
04H
Each particular bit of this register is set when the corresponding event occurs on the media during transmission of a packet. The contents of this register are not specified
until after the first transmission and are cleared upon the start of the next transmission initiated by the host. A read of this register is necessary after each transmission.
Bits
7
6
5
4
3
2
1 x
0
RTX
COL ABT CRS FU CDH OWC
P/N: PM0365
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MX98905B
12. TRANSMIT STATUS REGISTER (TSR) 04H (READ) (Continued)
SYMBOL PTX BIT D0 DESCRIPTION PACKET TRANSMITTED: Set when transmitted without error. (No excessive collisions or FIFO underrun) (abt = "0", FU = "0") Reserved TRANSMIT COLLIDED: Set when transmission collided at least once with another station on the network. The number of collisions is recorded in the Number of Collisions Registers (NCR). TRANSMIT ABORTED: Set when transmission is aborted because of excessive collisions. (Total number of transmission attempts equals 16). CARRIER SENSE LOST: Set when carrier is lost during transmission of a packet. Carrier Sense is monitored from the end of Preamble/Synch until TXEN is dropped. Note that transmission is not aborted on loss of carrier. FIFO UNDERRUN: Set when ENC cannot gain access of the bus before the FIFO empties. Transmission of the packet will be aborted. CD HEARTBEAT: Set when the transceiver fails to issue a collision signal after transmission of a packet. The Collision Detect (CD) heartbeat signal must commence during the first 6.4ms of the Interframe Gap following a transmission. In some collisions, however, the CD heartbeat bit will be set even when the transceiver is not performing the CD heartbeat test. OUT-OF-WINDOW COLLISION: Set when a collision occurred after a slot (51.2ms). Transmission will not be aborted. time
D1 COL D2
ABT
D3
CRS
D4
FU
D5
CDH
D6
OWC
D7
P/N: PM0365
58
REV. 1.3, NOV 20 ,1995
MX98905B
13. Receive Configuration Register (RCR) (WRITE) 0CH
This register determines what types of packets to be accepted and what mode the ENC will be in. The types include address type and error type. In the error type,
when any one bit of SEP and AR is clear and the packet received matches the condition set in SEP or AR, the packet is rejected.
Bits
7 x
6 x
5
4
3
2
1
0
SEP AR AB AM PRO MON
SYMBOL SEP
BIT D0
DESCRIPTION SAVE ERROR PACKETS. 0: Packets with CRC and Frame Alignment errors are rejected. 1: Packets with CRC and Frame Alignment errors are accepted.
AR
D1
ACCEPT RUNT PACKETS: This bit allows the receiver to accept packets that are smaller than 64 bytes. The packet must be at least 8 bytes long to be accepted as a runt. 0: Packets with fewer than 64 bytes rejected. 1: Packets with fewer than 64 bytes accepted.
AB
D2
ACCEPT BROADCAST: Enables the receiver to accept a packet with an all 1's destination address. 0: Packets with broadcast destination address rejected. 1: Packets with broadcast destination address accepted.
AM
D3
ACCEPT MULTICAST: Enables the receiver to accept a packet with a multicast address; all multicast addresses must pass the hashing array. 0: Packets with multicast destination address not checked. 1: Packets with multicast destination address checked.
P/N: PM0365
59
REV. 1.3, NOV 20 ,1995
MX98905B
13. RECEIVE CONFIGURATION REGISTER (RCR) 0CH (WRITE)
SYMBOL PRO BIT D4 DESCRIPTION PROMISCUOUS PHYSICAL: Enables the receiver to accept all packets with a physical address. 0: Physical address of mode must match the station address programmed in PAR0PAR5. 1: All packets with physical addresses accepted. MON D5 MONITOR MODE: Enables the receiver to check addresses and CRC on incoming packets without buffering to memory. The Missed Packet Tally Counter will be incremented for each recognized packet. 0: Packets buffered to memory. 1: Packets checked for address match, good CRC and frame alignment but not buffered to memory. RESERVED RESERVED D6 D7 Reserved Reserved
mode, bits D2, D3 and D4 should be set. In addition, the multicast hashing array must be set to all 1's in order to accept all multicast addresses.
Note: D2 and D3 are "OR'd" together, i.e., if D2 and D3 are set the
ENC will accept broadcast and multicast addresses as well as its own physical address. To establish full promiscuous
P/N: PM0365
60
REV. 1.3, NOV 20 ,1995
MX98905B
14. RECEIVE STATUS REGISTER (RSR) 0CH (READ) This register records status of the received packet. It includes information on errors, the type of address match, either physical or multicast, and the aborted packet type. The contents of this register are written to buffer memory by the DMA after receiving a good packet. If packets with errors are to be saved the receive status is written to memory at the head of the erroneous packet, when an erroneous packet is received. If packets with errors are to be rejected the RSR will not be written to memory. The contents will be cleared when the next packet arrives. CRC errors, frame alignment errors and missed packets are counted internally by the ENC, which relinquishes the host from reading the RSR in real time to record errors for Network Management Functions. The contents of this register are not specified until after the first reception.
Bits
7
6
5
4
3
2
1
0
PRX CRC FAE FO MPA PHY DIS DFR
SYMBOL PRX
BIT D0
DESCRIPTION PACKET RECEIVED CORRECTLY: Indicates packet received without error. (Bits CRC, FAE, FO and MPA are zero for the received packet.) Set when packets are received complete. CRC ERROR: Indicates packet received with CRC error. Increments Tally Counter (CNTR1). This bit will also be set for Frame Alignment errors. Set when packets are received complete. FRAME ALIGNMENT ERROR: Indicates that the incoming packet did not end on a byte boundary and the CRC did not match at last byte boundary. Increments Tally Counter (CNTR0). Set when packets are received complete. FIFO OVERRUN: This bit is set when the FIFO is not serviced causing overflow during reception. Reception of the packet will be aborted. MISSED PACKET: Set when packet intended for node cannot be accepted by ENC because of a lack of receive buffers, or if the controller is in monitor mode and did not buffer the packet to memory increments Tally Counter (CNTR2).
CRC
D1
FAE
D2
FO
D3
MPA
D4
P/N: PM0365
61
REV. 1.3, NOV 20 ,1995
MX98905B
14. RECEIVE STATUS REGISTER (RSR) 0CH (READ) (Continued)
SYMBOL PHY BIT D5 DESCRIPTION PHYSICAL/MULTICAST ADDRESS: Indicates whether received packet has a physical or multicast address type. Set/reset when Destination Address has been received. 0: Physical Address Match 1: Multicast/ Broadcast Address Match RECEIVER DISABLED: Set when receiver is disabled by entering Monitor mode. Reset when receiver is re-enabled when exiting the Monitor mode. DEFERRING: Set when CRS or COL inputs are active. If the transceiver has asserted the CD line as a result of the jabber, this bit will stay set indicating the jabber condition.
DIS
D6
DFR
D7
Note: The following coding applies to CRC and FAE bits FAE 0 0 1 1 CRC 0 1 0 1 Type of Error No Error (Good CRC and < 5 Dribble Bits) CRC Error Illegal, will not occur Frame Alignment Error and CRC Error
P/N: PM0365
62
REV. 1.3, NOV 20 ,1995
MX98905B
15. REGISTER ADDRESS ASSIGNMENTS (Continued)
PAGE 0 ADDRESS ASSIGNMENTS (PS1 = 0, PS0 = 0)
RA3-RA0 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH READ Command Register (CR) Current Local DMA Address 0 (CLDA0) Current Local DMA Address 1 (CLDA1) Boundary Pointer (BNRY) Transmit Status Register (TSR) Number of Collisions Register (NCR) FIFO (FIFO) Interrupt Status Register (ISR) WRITE Command Register (CR) Page Start Register (PSTART) Page Stop Register (PSTOP) Boundary Pointer (BNRY) Transmit Page Start Address (TPSR) Transmit Byte Count Register 0 (TBCR0) Transmit Byte Count Register 1 (TBCR1) Interrupt Status Register (ISR)
Current Remote DMA Address 0 (CRDA0) Remote Start Address Register 0 (RSAR0) Current Remote DMA Address 1 (CRDA1) Remote Start Address Register 1 (RSAR1) Reserved Reserved Receive Status Register (RSR) Tally Counter 0 (Frame Alignment Error) (CNTR0) Tally Counter 1 (CRC Error) (CNTR1) Tally Counter 2 (Missed Packet Error) (ENTR2) Remote Byte Count Register 0 (RBCR0) Remote Byte Count Register 1 (RBCR1) Receive Configuration Register (RCR) Transmit Configuration Register (TCR) Data Configuration Register (DCR) Interrupt Mask Register (IMR)
P/N: PM0365
63
REV. 1.3, NOV 20 ,1995
MX98905B
15. REGISTER ADDRESS ASSIGNMENTS (Continued)
PAGE 1 ADDRESS ASSIGNMENTS (PS1 = 0, PS0 = 1)
RA3-RA0 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH READ Command Register (CR) Physical Address Register 0 (PAR0) Physical Address Register 1 (PAR1) Physical Address Register 2 (PAR2) Physical Address Register 3 (PAR3) Physical Address Register 4 (PAR4) Physical Address Register 5 (PAR5) Current Page Register (CURR) Multicast Address Register 0 (MAR0) Multicast Address Register 1 (MAR1) Multicast Address Register 2 (MAR2) Multicast Address Register 3 (MAR3) Multicast Address Register 4 (MAR4) Multicast Address Register 5 (MAR5) Multicast Address Register 6 (MAR6) Multicast Address Register 7 (MAR7) WRITE Command Register (CR) Physical Address Register 0 (PAR0) Physical Address Register 1 (PAR1) Physical Address Register 2 (PAR2) Physical Address Register 3 (PAR3) Physical Address Register 4 (PAR4) Physical Address Register 5 (PAR5) Current Page Register (CURR) Multicast Address Register 0 (MAR0) Multicast Address Register 1 (MAR1) Multicast Address Register 2 (MAR2) Multicast Address Register 3 (MAR3) Multicast Address Register 4 (MAR4) Multicast Address Register 5 (MAR5) Multicast Address Register 6 (MAR6) Multicast Address Register 7 (MAR7)
P/N: PM0365
64
REV. 1.3, NOV 20 ,1995
MX98905B
15. REGISTER ADDRESS ASSIGNMENTS
PAGE 2 ADDRESS ASSIGNMENTS (PS1 = 1, PS0 = 0)
RA3-RA0 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH READ Command Register (CR) Page Start Register (PSTART) Page Start Register (PSTOP) Remote Next Packet Pointer Transmit Page Start Address (TPSR) Local Next Packet Pointer Address Counter (Upper) (ACU) Address Counter (Lower) (ACL) Reserved Reserved Reserved Reserved Receive Configuration Register (RCR) Transmit Configuration Register (TCR) Data Configuration Register (DCR) Interrupt Mask Register (IMR) WRITE Command Register (CR) Current Local DMA Address 0 (CLDA0) Current Local DMA Address 1 (CLDA1) Remote Next Packet Pointer Reserved Local Next Packet Pointer Address Counter (Upper) (ACU) Address Counter (Lower) (ACL) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Note: Page 2 registers should only be accessed for diagnostic purposes. They should not be modified during normal operation. Page 3 should never be modified.
P/N: PM0365
65
REV. 1.3, NOV 20 ,1995
MX98905B
REGISTER DESCRIPTION (Continued)
16. DMA REGISTERS The DMA Registers are partitioned into three groups: Transmit, Receive, and Remote DMA Registers, as the diagram shows on the next page. The Transmit group contains three registers: TPSR, TBCR0 and TBCR1. Registers in this group are used to initialize the Local DMA channel for transmission of packets. PSTART, PSTOP, CURR, BNRY, Receive Byte Counter, CLDA0 and CLDA1 are located in the receive group. They are used to initialize the Local DMA channel for packet reception. Meanwhile, the Page Start, Page Stop, Current and Boundary Registers are also used by the Buffer Management Logic to supervise the Receive Buffer Ring. The Remote DMA Registers are used to initialize the Remote DMA. Six registers are included: RSAR0, RSAR1, RBCR0, RBCR1, CRDA0 and CRDA1. The diagram on the next page shows 8- and 16-bit registers. For slave mode read/write, the 16-bit internal registers are also accessed as 8-bit registers by the host. Thus, the 16-bit Transmit Byte Count Register is broken into two 8-bit registers, namely, TBCR0 and TBCR1. Similarly, Remote Start Address and Remote Byte Count are broken into RSAR0, RSAR1, and RBCR0, RBCR1. Registers TPSR, PSTART, PSTOP, CURR and BNRY only check or control the upper 8 bits of address information on the bus. Thus, they are shifted to position 15-8, as shown in the diagram on the next page.
P/N: PM0365
66
REV. 1.3, NOV 20 ,1995
MX98905B
LOCAL DMA TRANSMIT REGISTERS BIT 15 TPSR TBCR 0, 1 PAGE START TRANSMIT BYTE COUNT LOCAL DMA CHANNEL 87 0
LOCAL DMA RECEIVE REGISTERS BIT 15 PSTART PSTOP VURR BNRY NOT READABLE CLDA 0, 1 PAGE START PAGE STOP CURRENT BPIMDARU RECEIVE BYTE COUNT CURRENT LOCAL DMA ADDRESS 87 0
REMOTE DMA REGISTERS BIT RSAR 0, 1 RBCR 0, 1 CRDA 0, 1 15 START ADDRESS REMOTE BYTE COUNT CURRENT REMOTE DMA ADDRESS DMA CHANNEL 87 0
P/N: PM0365
67
REV. 1.3, NOV 20 ,1995
MX98905B
16. DMA REGISTERS (Continued)
TRANSMIT DMA REGISTER (TPSR) This register points to the page where the assembled packet is ready to be transmitted. Only the eight higher order addresses are specified since all transmit packets are assembled on 256-byte page boundaries. The bit Bit assignment assignment is shown below. The values placed in bits D7D0 will be used to initialize the higher order address (A15A8) of the Local DMA for transmission while the lower order bits (A7-A0) are initialized to zero.
Bit 7 TPSR A15
Bit 6 A14
Bit 5 A13
Bit 4 A12
Bit 3 A11
Bit 2 A10
Bit 1 A9
Bit 0 A8
(A7-A0 initialized to zero)
TRANSMIT BYTE COUNT REGISTER 0, 1 (TBCR0, 1) These two registers indicate the length of the packet to be transmitted in bytes. The count must include the number of bytes in the source, destination, length and data fields (CRC field is exclusive). The maximum number of transmit bytes allowed is 64 kbytes. The ENC will not truncate transmissions whenever packet length is longer than 1500 bytes. Hence, in order to meet the IEEE 802.3 standard, software driver on upper layer must take care of maximum length problem by itself. The bit assignment is shown below:
Bit 7 TBCR1 L15
Bit 6 L14
Bit 5 L13
Bit 4 L12
Bit 3 L11
Bit 2 L10
Bit 1 L9
Bit 0 L8
Bit 7 TBCR0 L7
Bit 6 L6
Bit 5 L5
Bit 4 L4
Bit 3 L3
Bit 2 L2
Bit 1 L1
Bit 0 L0
P/N: PM0365
68
REV. 1.3, NOV 20 ,1995
MX98905B
16. DMA REGISTERS (Continued)
LOCAL DMA RECEIVE REGISTERS PAGE START/STOP REGISTERS (PSTART, PSTOP) The Page Start and Stop Registers program the starting and stopping page address of the Receive Buffer Ring. Since the ENC uses fixed 256-byte buffers aligned on page boundaries, only the upper eight bits of the start and stop address are specified. PSTART, PSTOP bit assignment.
PSTART, PSTOP
Bit 7 A15
Bit 6 A14
Bit 5 A13
Bit 4 A12
Bit 3 A11
Bit 2 A10
Bit 1 A9
Bit 0 A8
BOUNDARY REGISTER (BNRY) This register is used to prevent overflow of the Receive Buffer Ring. Buffer Management compares the contents of this register to the next buffer address when linking buffers together. If the contents of this register match the next buffer address, the Local DMA operation is aborted and the corresponding bit in ISR will be set.
Bit 7 BNRY A15
Bit 6 A14
Bit 5 A13
Bit 4 A12
Bit 3 A11
Bit 2 A10
Bit 1 A9
Bit 0 A8
CURRENT PAGE REGISTER (CURR) This register is used internally by the buffer management logic as a backup register for reception. CURR contains the address of the first buffer to be used for a packet reception, and is used to restore DMA pointers if receive errors occur. This register is initialized to the same value as PSTART and should not be written to unless the controller is reset.
Bit 7 CURR A15
Bit 6 A14
Bit 5 A13
Bit 4 A12
Bit 3 A11
Bit 2 A10
Bit 1 A9
Bit 0 A8
P/N: PM0365
69
REV. 1.3, NOV 20 ,1995
MX98905B
16. DMA REGISTERS (Continued)
CURRENT LOCAL DMA REGISTER 0, 1 (CLDA0, 1) The temporary local DMA address will be stored in these two registers after each burst transfer is completed. When another burst transfer is ready to start, values within these two registers will be loaded into the Address Counters (ACU and ACL) to generate address for local DMA channel. These two registers can be accessed to determine the current local DMA address.
Bit 7 CLDA1 A15
Bit 6 A14
Bit 5 A13
Bit 4 A12
Bit 3 A11
Bit 2 A10
Bit 1 A9
Bit 0 A8
Bit 7 CLDA0 A7
Bit 6 A6
Bit 5 A5
Bit 4 A4
Bit 3 A3
Bit 2 A2
Bit 1 A1
Bit 0 A0
REMOTE DMA REGISTER REMOTE START ADDRESS REGISTERS (RSAR0, 1) Remote DMA operations are programmed through the Remote Start Address (PSAR0, 1) and Remote Byte Count (RBCR0, 1) registers. The Remote Start Address is used to point to the start of the block of data to be transferred, while the Remote Byte Count is used to indicate the length of the block (in bytes)
Bit 7 RSAR1 A15
Bit 6 A14
Bit 5 A13
Bit 4 A12
Bit 3 A11
Bit 2 A10
Bit 1 A9
Bit 0 A8
Bit 7 RSAR0 A7
Bit 6 A6
Bit 5 A5
Bit 4 A4
Bit 3 A3
Bit 2 A2
Bit 1 A1
Bit 0 A0
P/N: PM0365
70
REV. 1.3, NOV 20 ,1995
MX98905B
16. DMA REGISTER (Continued)
REMOTE BYTE COUNT REGISTERS (RBCR0, 1)
Bit 7 RBCR1 BC15
Bit 6 BC14
Bit 5 BC13
Bit 4 BC12
Bit 3 BC11
Bit 2 BC10
Bit 1 BC9
Bit 0 BC8
Bit 7 RBCR0 BC7
Bit 6 BC6
Bit 5 BC5
Bit 4 BC4
Bit 3 BC3
Bit 2 BC2
Bit 1 BC1
Bit 0 BC0
Note: - RSAR1 programs the start address bits A8-A15 - RSAR0 programs the start address bits A0-A7 - Address incremented by two for word transfers, and by one for byte transfers
- - -
RBCR1 programs MSB byte count RBCR0 programs LSB byte count Byte count decremented by two for word transfers, and by one for byte transfers
CURRENT REMOTE DMA ADDRESS (CRDA0, 1) The Current Remote DMA Registers contain the current address of the Remote DMA. CRDA1/0 are similar to CLDA1/0 except that CRDA1/0 store the temporary address of the Remote DMA. The bit assignment is shown below:
Bit 7 CRDA1 A15
Bit 6 A14
Bit 5 A13
Bit 4 A12
Bit 3 A11
Bit 2 A10
Bit 1 A9
Bit 0 A8
Bit 7 CRDA0 A7
Bit 6 A6
Bit 5 A5
Bit 4 A4
Bit 3 A3
Bit 2 A2
Bit 1 A1
Bit 0 A0
P/N: PM0365
71
REV. 1.3, NOV 20 ,1995
MX98905B
16. DMA REGISTER (Continued)
FIFO This is an 8-bit register which allows the CPU to examine the contents of the FIFO after loopback. The FIFO will contain the last 8 data bytes transmitted in the loopback packet. Sequential reads from the FIFO will advance a pointer in the FIFO automatically and reading of all 8 bytes.
Bit 7 FIFO DB7
Bit 6 DB6
Bit 5 DB5
Bit 4 DB4
Bit 3 DB3
Bit 2 DB2
Bit 1 DB1
Bit 0 DB0
Note: The FIFO should only be read when the ENC has been programmed in the loopback mode.
P/N: PM0365
72
REV. 1.3, NOV 20 ,1995
MX98905B
ABSOLUTE MAXIMUM RATINGS
RATING Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Storage Temperature Range (TSTG) Power Dissipation (PD) Lead Temp. (TL) (Soldering, 10 sec.) ESD rating (RZAP=1.5K, CZAP=120pF) 1600V 500 mW 260C VALUE 4.75V to +5.5V -0.5V to VCC +0.5V -0.5V to VCC +0.5V -65 to +150C C NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability.
DC CHARACTERISTICS
SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS
SUPPLY CURRENT
ICC Average Active (Transmitting/Receiving) 10 Supply Current ICCIDLE Average Idle Supply Current 10 100 mA 100 mA X1=20MHz Clock VIN=Switching X1=20MHz Clock VIN=VCC or GND LCCLP Low Power Supply Current 10 80 uA X1=Undriven
TTL INPUTS
VIL VIH IIN Maximum Low Level Input Voltage Minimum High Level Input Voltage INput Current 2.0 -1.0 1.0 uA 0.8 V V VI=VCC of GND
3SH TRI-STATE HIGH DRIVE I/O
VOH VOL VIL VIH IIN IOZ Minimum High Level Output Voltage Maximum Low Level Output Voltage Maximum Low Level Input Voltage Minimum High Level Input Voltage Input Current Maximum TRI-STATE Output Leakage Current 2.0 -1.0 -10.0 1.0 10.0 2.4 0.5 0.8 V V V V uA uA VI=VCC or GND VOUT=VCCor GND IOH=-3mA IOL=24mA
P/N: PM0365
73
REV. 1.3, NOV 20 ,1995
MX98905B
DC CHARACTERISTICS (Continued)
SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS
MOS INPUTS, OUTPUTS AND I/O
VOH VOL VIL VIH IIN IIN Minimum High Level Output Voltage Maximum Low Level Output Voltage Maximum Low Level Input Voltage Minimum Low Level Input Voltage Input Current Input Current TEST, DWID Pulldown Register IOZ Maximum TRI-STATE Output Leakage Current -10.0 10.0 uA VOUT=VCC or GND 2.0 -1.0 50 1.0 2000 VCC-0.1 0.1 0.8 V V V V uA uA VI=VCC or GND VI=VCC IOH=-20uA IOL=20uA
OCH COLLECTOR HIGH DRIVE OUTPUT
VOL Maximum Low Level Output Voltage 0.5 V IOL=24mA
LED DRIVER OUTPUT
VOL Maximum Low Level Output Voltage 0.5 V IOL=16mA
THIN DRIVER OUTPUT
VOH VOL Minimum High Level Output Voltage Maximum Low Output Voltage 2.4 0.5 V V IOH=-8mA IOL=2mA
OSCILLATOR PINS (X1 AND X2)
VIH X1 Input High Voltage 2.0 V X1 is connected to an oscillator VIL X1 Input Low Voltage 0.8 V X1 is connected to an oscillator IOSC X1 Input Current 1 mA X1 is connected to an oscillator VIN=VCC or GND
P/N: PM0365
74
REV. 1.3, NOV 20 ,1995
MX98905B
DC CHARACTERISTICS (Continued)
SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS
AUI
VOD Differential Output Voltage (TX) 550 1250 MV 78 ohm Termination and 270 ohm from each to GND VOB Differential Idle Output Voltage Typical : 40mV mV 78 ohm Termination and 270 ohm from each to GND VU Undershoot Voltage (TX) Typical : 80mV mV 78 ohm Termination and 270 ohm from each to GND VDS VCM Diff. Squelch Threshold (RX, CD) Diff. Input Common Mode Voltage (RX, CD) -175 0 -300 5.25 mV V
TPI
RTOL TXOD, TXO Low Level Output Resistance RTOH TXOD, TXO High Level Output Resistance VSRON1 Receive Threshold Turn-On Voltage 10BASE-T Mode VSRON1 Receive Threshold Turn-Off Voltage Reduced Threshold VSROFF VDIFF Receive Threshold Turn-Off Voltage Differential Mode Input Voltage Range 75 -3.1 300 3.1 mV V VCC=5.0V 75 300 mV 300 -585 mV 15 ohm OH=-25mA 15 ohm IOL=25mA
P/N: PM0365
75
REV. 1.3, NOV 20 ,1995
MX98905B
AC CHARACTRISTICS
SYMBOL T1 T2 T3 T4 T5 T6 T7 PARAMETER EECS setup to SK EECS hold after SK MSD2 Low time MSD2 High time MSD2 Clock period Data In, setup to MSD2 high Data In hold from MSD2 high MIN. 300 300 500 500 1 200 300 MAX. UNIT ns ns ns ns ms ns ns
SERIAL EEPROM TIMING
EECS
T1
T5
T2
MDMD2
T4 T6 T3 T7
MEMD1
MDMD0
P/N: PM0365
76
REV. 1.3, NOV 20 ,1995
MX98905B
AC CHARACTRISTICS
SYMBOL T1 T2 T3 T4 T5 PARAMETER MEMA1-15 valid before RSCXL Asserted (Note1) MEMA1-15 Valid before MSRD/MSWR asserted MSRDL-WRL Width MEMA1-15 Valid to MSRDL or MSWRL Deasserted MEMA1-15 Valid after MSRDL-WRL Deasserted T6 RCSXL Held after MSRDL-WRL Deasserted (Note1) T7 T8 T9 T10 T11 T12 T13 T14 RCXL and MEMA1-15 valid to MEMD0-15 valid Read Data Hold from MSRDL Deasserted Write Data Set-Up to MSWRL Deasserted Write Data Held from MSWRL Deasserted Time Between Transfers Minimum bus Clock High Time (bch) Minimum Bus Clock Low Time (bcl) Minimum Bus Clock Cycle Time (bcyc) 0 60 10 4 10 20 50 100 ns ns ns ns bcyc ns ns ns 200 400 ns 20 2 40 10 MIN. MAX. 30 UNIT ns ns bcyc ns ns
Note 1 : In 8-bit mode RCSXL refers to RCS1L only. In 16-bit mode RCSXL refers to both RCS1L and RCS2L.
MEMORY SUPPORT BUS ACCESSES (FOR I/O PORT OR FIFO TRANSFERS)
t1
t2
t3
t4
t1
T12
T13
BSCK
T14 T11
MEMA1-15
T5 T1 T4 T6
RCSXL
T2
T3
MSRDL or MSWRL
T7 T8
MEMD0-15 (READ)
T9 T10
MEMD0-15 (WRITE)
P/N: PM0365 REV. 1.3, NOV 20 ,1995
77
MX98905B
ISA SLAVE ACCESSES
T6C
T16
BALE
T1 T15 T19 T18
AEN
T2 T22
LA17-23
T21 T6A, B
SBHE SA0-9
T13 T7
MRDL, MWRL, SMRDL, SMWRL, IORDL, IOWRL
T8 T14
M16L, IO16L
T5B
T5A T23 T5C
CHRDY
T3 T4 T17 T10
SD0-15 (READ)
T20 T9 T11
SD0-15 (WRITE) RCSXL or BPCSL
T27 T35
DATA VALID T30 T12
T28
T36 T31
MSRDL, MSWRL
T29 T34 T37
T32
MEMA1-15
ADDRESS VALID
T24
T25
MEMD0-15 (READ)
T38 T26 T33
MEMD0-15 (WRITE)
P/N: PM0365
78
REV. 1.3, NOV 20 ,1995
MX98905B
AC CHARACTRISTICS
SYMBOL PARAMETER 8 BIT MIN. T1 T2 BALE width AEN valid before command strobe active T3 SBHEL & SA0-9 valid before command asserted T4 IORDL, MRDL asserted to SD0-15 driven (Note 3) T5a SBHEL & SA0-9 valid before IO16L valid (Notes 1 & 9) T5b T5c LA17-23 valid to M16L valid (Note 1) SBHEL & SA0-9 valid and IORDL or IOWRL active before IO16L valid (Notes 1 & 10) T6a IORDL, IOWRL asserted to CHRDY negated (Notes 2 & 5) T6b MRDL, MWRL asserted to CHRDY negated (Note 2) T6c BALE asserted & SA0-9 valid to CHRDY negated (Notes 2 & 4) T7 IORDL deasserted before SBHEL & SA0-9 invali T8 T9 LA17-23 invalid to M16L invalid (Note 1) IORDL, MRDL deasstered to SD0-15 (Note 3)Read Data Invalid T10 IORDL, MRDL deasserted to SD0-15 floating (Note 3) T11 D0-15 write data valid to IOWRL deasstered (Note 3) T12 IOWRL, MWRL negated to SD0-15 write data 15 invalid (Note 3) T13a T14a T14b IORDL, IOWRL Active width (Note 3) IORDL, IOWRL inactive width MRDL, MWRL inactive width SMRDL, SMWRL 300 85 140 85 ns ns 15 ns 60 20 ns 30 30 ns 0 0 0 ns ns 15 15 ns 15 15 ns 35 35 ns 35 35 ns 30 20 ns ns 45 ns 0 0 ns 20 20 ns 20 40 MAX. 16 BIT MIN. 20 40 MAX. ns ns UNIT
P/N: PM0365
79
REV. 1.3, NOV 20 ,1995
MX98905B
AC CHARACTRISTICS (Continued)
SYMBOL PARAMETER 8 BIT MIN. T15 BALE asserted before MRDL, MWRL asserted T16 MRDL, MWRL deasserted before next BALE asserted T17 CHRDY asserted to SD0-15 I/O read data valid (Notes 2, 3, & 6) T18 T19 T20 IORDL, IOWRL negated before AEN invalid AEN valid before BALE deassereted IORDL asserted to SD0-15 read data valid (Notes 3 & 7) T21 T22 T23 T24 LA17-23 valid before BALE negated BALE negated before LA17-23 invalid LA17-23 valid before MRDL, MWRL asserted Read data valid on MSD0-15 to valid on SD0-15 T25 MSRDL deasserted to MSD0-15 read data Invalid (Note 3) T26 Write data valid on SD0-15 to valid on MEMD0-15 T27 SA0-19 valid to /RCS XL or /BPCSL asserted 40 (Note 11) T28 MRDL, MWRL asserted to MSRDL, MSWRL asserted T29 T30 SA0-19 valid to MEMA1-15 valid SA0-19 invalid to RCSXL or BPCSL negated 30 (Note 11) T31 MRDL, MWRL deasserted to MSRDL, MSWRL deasserted T32 MSWRL deasserted to MEMA1-15 invalid 10 10 ns 0 30 0 45 ns 30 20 30 ns ns 30 30 ns 40 ns 30 30 ns 0 40 0 40 ns ns 150 150 ns 25 50 50 25 ns ns 60 60 ns 20 ns MAX. 16 BIT MIN. 25 MAX. ns UNIT
P/N: PM0365
80
REV. 1.3, NOV 20 ,1995
MX98905B
AC CHARACTRISTICS (Continued)
SYMBOL PARAMETER 8 BIT MIN. T33 MSWR1deasserted to MSMD0-15 invalid (Note 3) T34 MEMA1-15 valid before /MSWRL asserted T35 RCSXL or /BPCSL asserted to CHRDY asserted (Note 11) T36 MSRDL, MSWRL asserted to CHRDY asserted T37 T38a MEMA1-15 valid to CHRDY asserted Driving data from SD0-15 on to MEMD0-15 to CHRDY asserted for RAM access T38b Driving data from SD0-15 to CHRDY asserted for Boot PROM access 260 260 ns 15 60 15 60 ns ns 0 0 ns 15 15 ns 20 20 ns 20 MAX. 16 BIT MIN. 20 MAX. ns UNIT
Note 1: M16L, IO16 are only asserted for 16-bit transfers. Note 2: CHRDY is only deasserted if the NIC core cannot service the access immediately. It is held deasserted until the NIC core is ready, causing the system to insert wait states. Note 3: On 8-bit trnasfers only 8 bits of MEHD0-15 and D0-7 are driven. Note 4: This is the earty CHRDY timing required by some machines, where CHRDY is referenced to BALE. In this mode of operation, under certain circumstances, CHRDY will be asserted for cycles which are not for this device i.e., memory cycles or I/O cycles where SA0-9 match our address before reaching their valid state. In such a case the time to assert CHRDY, from MRDL, MWRL or SA0-9 invalid, will be the same as the deassertion time specified. Note 5: This is the standard CHRDY timing where CHRDY is asserted after IORDL or IOWRL. Note 6: Read data valid is referenced to CHRDY when wait states have been inserted. Note 7: If no wait states are inserted read data valid can be measured from IORDL. Note 8: This is a minimum timing with no additional wait states. Note 9: This is the standard I/O 16 timing where /IO16 is asserted after a valid address decode and IORDL or IOWRL going active. Note 10: This is the late IO16L timing, required by some machines. Where IO16L is asserted after a valid address decode and IORDL or IOWRL going active. Note 11: BPCS is asserted for a boot PROM access. RCSL for a RAM access. RCSXL refers to RCS1L and RCS2L Depending on the mode of operation either or both can be asserted. See the Functional Bus Timing section for further explanation. Note 12: Specifications which measure delays from an active state to a high impedance state are not guaranteed by production test, but are characterized and correlated to determine true driver turn-off time by simulating inherent R-C delay times. In test measurements.
P/N: PM0365
81
REV. 1.3, NOV 20 ,1995
MX98905B
AC CHARACTERISTICS (Continued)
SYMBOL tTOH tTOL PARAMETER Transmit Output High before (Half Step) Transmit Output Idle Time (Half Step) MIN. 200 8000 MAX. UNIT ns ns
AUI TRANSMIT TIMING (END-OF-PACKET)
tTOI
1 0 0
tTOH
TXP TXM
1 0 1
TXP TXM
SYMBOL tEOP1
PARAMETER Receive End-Of-Packet Hold Time after Logic "1" (Note 1)
MIN. 250
MAX.
UNIT ns
tEOP 0
Receive End-Of-Packet Hold Time after Logic "0" (Note 1)
250
ns
NOTE: 1. This parameter is guaranteed by design and is not tested.
AUI/API RECEIVE END-OF-PACKET TIMING
1 RXP or RXIP
1
tEOP1
RXM or RXIM
0
0
RXP or RXIP
tEOP0
RXM or RXIM
P/N: PM0365
82
REV. 1.3, NOV 20 ,1995
MX98905B
AC CHARACTERISTICS (Continued)
SYMBOL tDEL PARAMETER Pre-Emphasis Output Delay (TXOP,TXOM to TXODP,TXODM) (Note 1) tOFF Transmit Hold Time at End-Of-Packet (TXOP,TXOM) (Note 1) tOFFD Transmit Hold Time at End-Of-Packet (TXODP,TXODM) (Note 1)
NOTE: 1. tested. This parameter is guaranteed by design and is not
MIN. 46
MAX. 54
UNIT ns
250
ns
200
ns
TPI TRANSMIT AND END-OF-PACKET TIMING
1
0
1
TXOP tDEL tOFF
TXODP tOFFD
TXOM tDEL TXODM 1 1 0
TXOP tOFF
TXODP tOFFD
TXOM
TXODM
P/N: PM0365
83
REV. 1.3, NOV 20 ,1995
MX98905B
AC CHARACTERISTICS (Continued)
SYMBOL tIP tIPW PARAMETER Time between Link Output Pulses Link Integrity Output Pulse Width MIN. 8 80 MAX. 24 130 UNIT ms ns
LINK PULSE TIMING
tIPW
tIP
TXOP
TXODP
TXOM
TXODM
ORDERING INFORMATION
PART NO. MX98905BFC PACKAGE 160 Pin PQFP
P/N: PM0365
84
REV. 1.3, NOV 20 ,1995
MX98905B
PACKAGE INFORMATION
160-Pin PQFP
A B
ITEM A B C D E F G H I J K L M N O
MILLIMETERS 31.20 .30 28.00 .10 28.00 .10 31.20 .30 25.35 1.33 [REF] 1.33 [REF] .30 [Typ.] .65 [Typ.] 1.60 [REF] .80 .20 .15 [Typ.] .10 max. 3.35 max. .10 min.
INCHES 1.228 .012 1.102 .004 1.102 .004 1.228 .012 .999 .052 [REF] .052 [REF] .12 [Typ.] .026 [Typ.] .063 [REF] .031 .008 .006 [Typ.] .004 max. .132 max. .004 min.
F 160 1 41 40 E C D 120 121 81 80
NOTE: Each lead centerline is located within .25mm[.01 inch] of its true position [TP] at a maximum material condition.
G H I J N L M K O P
P/N: PM0365
85
REV. 1.3, NOV 20 ,1995
MX98905B
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688 FAX:+886-3-563-2888
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TEL:+32-2-456-8020 FAX:+32-2-456-8021
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MACRONIX AMERICA, INC.
TEL:+1-408-453-8088 FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900 FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
86

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